Comparing files front.abl and ..\fpanel\front.abl
****** front.abl
!omni_data_out PIN istype 'buffer';
!omni_data_in  PIN istype 'buffer';

****** ..\fpanel\front.abl
!omni_data_out PIN istype 'buffer';

******

****** front.abl
ma = [ma0..ma11];
!ma_in PIN istype 'buffer';

****** ..\fpanel\front.abl
ma = [ma0..ma11];

******

****** front.abl

" In command mode we ack for all, in data mode each acks for self= "
periph_ack.clk = clk7d5;
periph_ack.t = !periph_ack & (!ack_rev & host_clk_cnt1 & host_clk_cnt0 &
         !host_clk_d2 & (our_addr &
           (!write_break # write_break & !write_break_pending) #
           !host_ack & our_addr_bits) # ack_rev) #
     periph_ack & (!ack_rev & host_clk_cnt1 & host_clk_cnt0 & host_clk_d2 #
         ack_rev & !rev_req_cnt1 & !rev_req_cnt0);

****** ..\fpanel\front.abl

"If not our addr then leave ack high"
periph_ack.clk = clk7d5;
"periph_ack.t = !periph_ack & (!ack_rev & host_clk_cnt1 & host_clk_cnt0 &
"         !host_clk_d2 & (our_addr &
"           (!write_break # write_break & !write_break_pending) #
"           !host_ack & our_addr_bits) # ack_rev) #
"     periph_ack & our_addr &
"        (!ack_rev & host_clk_cnt1 & host_clk_cnt0 & host_clk_d2 #
"         ack_rev & !rev_req_cnt1 & !rev_req_cnt0) #
"     !periph_ack & !our_addr;
periph_ack.t = !periph_ack;

******

****** front.abl

   "This may cause bus contention on turnaround"
omni_data_in = !omni_data_out &
   !(sr_to_data # our_break.fb & write_break & ts2);
omni_data_out = sr_to_data # our_break.fb & write_break & ts2;
****** ..\fpanel\front.abl


omni_data_out = sr_to_data # our_break.fb & write_break & ts2;
******

****** front.abl
ma.oe = our_break.fb;
ma_in = read_leds & (rx_byte_1 # rx_byte_2 # rx_byte_3);
[ma0..ma11] := [ma0.fb,ma1.fb,ma2.fb,ma3.fb,pdata7..pdata0] &
****** ..\fpanel\front.abl
ma.oe = our_break.fb;
[ma0..ma11] := [ma0.fb,ma1.fb,ma2.fb,ma3.fb,pdata7..pdata0] &
******


