 
XACT:  version M1.5.25                           Xilinx Inc.
                                  Fitter Report
   Design Name: fpanel2
Fitting Status: Successful                          Date:  3- 7-1999,  1:54PM

****************************  Resource Summary  ****************************

Design        Device            Macrocells     Product Terms   Pins            
Name          Used              Used           Used            Used            
fpanel2       XC95216-15-PQ160  150/216 ( 69%) 503/1080 ( 46%)  109/133 ( 81%) 

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   32          32    |  I/O              :   103       22
Output        :   38          38    |  GCK/IO           :     3        0
Bidirectional :   35          35    |  GTS/IO           :     2        2
GCK           :    3           3    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total    109         109

GLOBAL RESOURCES:

Signal 'clk7d5' mapped onto global clock net GCK1.
Signal 'int_strobe' mapped onto global clock net GCK2.
Signal 'tp3' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Signal 'initialize' mapped onto global set/reset net GSR1.

POWER DATA:

There are 150 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 150 macrocells used (MC).

End of Resource Summary
****************************  Errors and Warnings  *************************

WARNING:xr5030 - Constant signal value '1' drives output signal 
'periph_req'.
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
ack_rev             3       7       FB10_2  STD  SLOW 113  I/O       O
bk_cycle            2       5       FB9_5   STD  SLOW 76   I/O       O
bk_data_cont        1       4       FB8_5   STD  SLOW 129  I/O       O
bk_in_prog          2       2       FB11_2  STD  SLOW 87   I/O       O
break_done_Q        1       2       FB6_6   STD       144  I/O       I
break_prio          1       2       FB9_11  STD  SLOW 82   I/O       O
byte_cnt0_Q         2       3       FB4_18  STD            (b)       (b)
byte_cnt1_Q         2       4       FB4_16  STD            (b)       (b)
cpma_disable        2       2       FB11_5  STD  SLOW 89   I/O       O
cpma_disable_COM/cpma_disable_COM_SETF__$INT
                    1       2       FB9_7   STD            (b)       (b)
data_mode_Q         2       5       FB2_16  STD            (b)       (b)
dbk_data0_Q         2       3       FB12_10 STD            (b)       (b)
dbk_data10_Q        2       3       FB8_10  STD            (b)       (b)
dbk_data11_Q        2       3       FB12_8  STD       105  I/O       (b)
dbk_data1_Q         2       3       FB12_7  STD            (b)       (b)
dbk_data2_Q         2       3       FB9_9   STD       79   I/O       I
dbk_data3_Q         2       3       FB8_9   STD       132  I/O       (b)
dbk_data4_Q         2       3       FB4_13  STD            (b)       (b)
dbk_data5_Q         2       3       FB4_11  STD       159  GSR/I/O   GSR/I
dbk_data6_Q         2       3       FB8_7   STD            (b)       (b)
dbk_data7_Q         2       3       FB8_6   STD       130  I/O       (b)
dbk_data8_Q         2       3       FB8_4   STD            (b)       (b)
dbk_data9_Q         2       3       FB8_3   STD       128  I/O       (b)
delay_cnt0_Q        2       7       FB10_12 STD       122  I/O       I
delay_cnt1_Q        3       7       FB10_16 STD            (b)       (b)
delay_cnt2_Q        4       7       FB10_18 STD            (b)       (b)
delay_cnt3_Q        4       7       FB10_17 STD       125  I/O       (b)
delay_cnt4_Q        3       7       FB10_14 STD       123  I/O       (b)
delay_cnt5_Q        2       7       FB10_10 STD            (b)       (b)
disk_addr0_Q        4       12      FB11_18 STD            (b)       (b)
disk_addr10_Q       4       12      FB8_18  STD            (b)       (b)
disk_addr11_Q       4       12      FB8_17  STD       139  I/O       I
disk_addr1_Q        4       12      FB8_16  STD            (b)       (b)
disk_addr2_Q        4       12      FB8_15  STD       138  I/O       I
disk_addr3_Q        4       12      FB11_17 STD       98   I/O       I
disk_addr4_Q        4       12      FB11_16 STD            (b)       (b)
disk_addr5_Q        4       12      FB11_15 STD       97   I/O       I
disk_addr6_Q        4       12      FB11_13 STD            (b)       (b)
disk_addr7_Q        4       12      FB11_12 STD       95   I/O       I
disk_addr8_Q        4       12      FB11_10 STD            (b)       (b)
disk_addr9_Q        4       12      FB8_13  STD            (b)       (b)
ema0                3       11      FB4_5   STD  SLOW 154  I/O       I/O
ema1                3       11      FB4_6   STD  SLOW 155  I/O       I/O
ema2                3       11      FB4_8   STD  SLOW 156  I/O       I/O
host_clk_cnt0_Q     3       4       FB2_18  STD            (b)       (b)
host_clk_cnt1_Q     3       4       FB2_17  STD       17   I/O       I
host_clk_d1_Q       2       3       FB10_9  STD       118  I/O       (b)
host_clk_d2_Q       1       1       FB2_7   STD            (b)       (b)
ind1                3       6       FB12_2  STD  SLOW 101  I/O       O
ind2                3       5       FB12_5  STD  SLOW 103  I/O       O
init_out            1       4       FB8_8   STD  SLOW 131  I/O       O
key_cntrl           2       4       FB12_9  STD  SLOW 106  I/O       O
latch_led0_Q        6       8       FB9_1   STD            (b)       (b)
latch_led10_Q       6       8       FB9_18  STD            (b)       (b)
latch_led11_Q       6       8       FB9_17  STD       86   I/O       I
latch_led1_Q        6       8       FB9_15  STD       85   I/O       (b)
latch_led2_Q        6       8       FB9_13  STD            (b)       (b)
latch_led3_Q        6       8       FB12_1  STD            (b)       (b)
latch_led4_Q        6       8       FB12_18 STD            (b)       (b)
latch_led5_Q        6       8       FB12_17 STD       112  I/O       (b)
latch_led6_Q        6       13      FB9_12  STD       83   I/O       (b)
latch_led7_Q        6       11      FB12_14 STD       109  I/O       (b)
latch_led8_Q        6       8       FB9_10  STD            (b)       (b)
latch_led9_Q        6       8       FB12_13 STD            (b)       (b)
latch_led9_Q/latch_led9_Q_CLKF
                    5       5       FB6_18  STD            (b)       (b)
load_addr           1       3       FB8_11  STD  SLOW 133  I/O       O
load_addr_en        1       3       FB8_14  STD  SLOW 135  I/O       O
ma0                 4       23      FB1_2   STD  SLOW 18   I/O       I/O
ma1                 4       22      FB1_6   STD  SLOW 22   I/O       I/O
ma10                4       13      FB1_3   STD  SLOW 19   I/O       I/O
ma11                4       12      FB1_5   STD  SLOW 21   I/O       I/O
ma2                 4       21      FB1_8   STD  SLOW 23   I/O       I/O
ma3                 4       20      FB1_17  STD  SLOW 30   I/O       I/O
ma4                 4       19      FB1_11  STD  SLOW 25   I/O       I/O
ma5                 4       18      FB1_12  STD  SLOW 26   I/O       I/O
ma6                 4       17      FB6_2   STD  SLOW 140  I/O       I/O
ma7                 4       16      FB1_14  STD  SLOW 27   I/O       I/O
ma8                 4       15      FB1_15  STD  SLOW 28   I/O       I/O
ma9                 4       14      FB1_16  STD  SLOW 29   I/O       I/O
ma_in               2       6       FB10_6  STD  SLOW 116  I/O       O
ma_inc_Q            1       2       FB6_5   STD       143  I/O       I
ma_ms_load          2       2       FB9_2   STD  SLOW 72   I/O       O
md_dir              1       6       FB9_14  STD  SLOW 84   I/O       O
mem_start           2       4       FB8_2   STD  SLOW 126  I/O       O
ms_ir_dis           2       3       FB12_12 STD  SLOW 108  I/O       O
need_break_Q        3       12      FB6_17  STD       151  I/O       (b)
omni_data0          5       11      FB2_6   STD  SLOW 9    I/O       I/O
omni_data1          5       11      FB5_6   STD  SLOW 49   I/O       I/O
omni_data10         5       11      FB5_3   STD  SLOW 47   I/O       I/O
omni_data11         5       11      FB5_5   STD  SLOW 48   I/O       I/O
omni_data2          5       11      FB5_8   STD  SLOW 50   I/O       I/O
omni_data3          5       11      FB5_9   STD  SLOW 52   I/O       I/O
omni_data4          5       11      FB5_11  STD  SLOW 53   I/O       I/O
omni_data5          5       11      FB2_8   STD  SLOW 11   I/O       I/O
omni_data6          5       11      FB2_9   STD  SLOW 12   I/O       I/O
omni_data7          5       11      FB2_11  STD  SLOW 13   I/O       I/O
omni_data8          5       11      FB2_12  STD  SLOW 14   I/O       I/O
omni_data9          5       11      FB5_12  STD  SLOW 54   I/O       I/O
omni_data_in        2       7       FB6_8   STD  SLOW 145  I/O       O
omni_data_out       2       7       FB6_14  STD  SLOW 149  I/O       O
omni_data_out_COM/omni_data_out_COM_D2__$INT
                    2       7       FB6_15  STD       150  I/O       (b)
our_addr            5       9       FB2_14  STD  SLOW 15   I/O       O
our_break           2       5       FB9_8   STD  SLOW 78   I/O       O
our_break_del_Q     2       3       FB6_13  STD            (b)       (b)
our_break_tp1_Q     2       2       FB6_12  STD       148  I/O       I
par_rx_rising_Q     1       5       FB2_5   STD       8    GTS/I/O   (b)
pdata0              10      16      FB3_2   STD  SLOW 32   I/O       I/O
pdata1              10      16      FB3_8   STD  SLOW 36   I/O       I/O
pdata2              10      16      FB7_2   STD  SLOW 58   I/O       I/O
pdata3              10      16      FB7_6   STD  SLOW 62   I/O       I/O
pdata4              7       13      FB3_11  STD  SLOW 38   I/O       I/O
pdata5              7       13      FB5_2   STD  SLOW 45   I/O       I/O
pdata6              7       13      FB4_17  STD  SLOW 5    I/O       I/O
pdata7              7       13      FB4_3   STD  SLOW 153  I/O       I/O
periph_ack          8       17      FB2_3   STD  SLOW 7    I/O       O
periph_clk          5       10      FB7_11  STD  SLOW 65   I/O       O
periph_req          0       0       FB11_11 STD  SLOW 93   I/O       O
read_break_pending_Q
                    3       6       FB6_16  STD            (b)       (b)
reg_num0_Q          2       6       FB10_8  STD       117  I/O       I
reg_num1_Q          2       6       FB10_7  STD            (b)       (b)
reg_num2_Q          2       6       FB10_5  STD       115  I/O       I
rev_req_cnt0        2       3       FB10_11 STD  SLOW 119  I/O       O
rev_req_cnt1        2       3       FB10_15 STD  SLOW 124  I/O       O
rev_req_sync        1       1       FB11_14 STD  SLOW 96   I/O       O
sr_to_data          3       14      FB12_11 STD       107  I/O       (b)
stop                2       3       FB11_8  STD  SLOW 91   I/O       O
sw_cycle_Q          4       6       FB8_12  STD       134  I/O       I
sw_halt_Q           2       10      FB1_18  STD            (b)       (b)
sw_momentary0_Q     2       10      FB5_18  STD            (b)       (b)
sw_momentary1_Q     2       10      FB1_13  STD            (b)       (b)
sw_momentary2_Q     2       10      FB6_11  STD       147  I/O       (b)
sw_pulse_Q          3       8       FB10_13 STD            (b)       (b)
sw_rotary0_Q        2       10      FB6_10  STD            (b)       (b)
sw_rotary1_Q        2       10      FB6_9   STD       146  I/O       I
sw_rotary2_Q        2       10      FB6_7   STD            (b)       (b)
sw_start_Q          2       10      FB2_13  STD            (b)       (b)
sw_start_d1_Q       2       3       FB8_1   STD            (b)       (b)
sw_start_d2_Q       1       1       FB11_9  STD       92   I/O       I
sw_step_Q           2       10      FB2_10  STD            (b)       (b)
sw_sw               2       10      FB2_15  STD  SLOW 16   I/O       O
test_reg0           2       10      FB3_15  STD  SLOW 43   I/O       O
test_reg1           2       10      FB5_14  STD  SLOW 55   I/O       O
test_reg2           2       10      FB7_15  STD  SLOW 68   I/O       O
test_reg3           2       10      FB5_15  STD  SLOW 56   I/O       O
test_reg4           2       10      FB4_9   STD  SLOW 158  I/O       O
test_reg5           2       10      FB4_12  STD  SLOW 2    GTS/I/O   O
test_reg6           2       10      FB4_14  STD  SLOW 3    I/O       O
test_reg7           2       10      FB4_15  STD  SLOW 4    GTS/I/O   O
write_break_pending_Q
                    2       9       FB10_4  STD            (b)       (b)
xflag               1       1       FB12_15 STD  SLOW 111  I/O       O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
clk7d5                              FB3_3             33   GCK/I/O   GCK/I
ecp_mode                            FB9_9             79   I/O       I
fset                                FB9_6             77   I/O       I
host_ack                            FB7_8             63   I/O       I
host_clk                            FB5_17            57   I/O       I
initialize                          FB4_11            159  GSR/I/O   GSR/I
int_strobe                          FB3_6             35   GCK/I/O   GCK
ir0                                 FB6_6             144  I/O       I
ir1                                 FB11_17           98   I/O       I
ir2                                 FB8_12            134  I/O       I
md0                                 FB11_15           97   I/O       I
md1                                 FB6_9             146  I/O       I
md10                                FB12_3            102  I/O       I
md11                                FB10_8            117  I/O       I
md2                                 FB2_17            17   I/O       I
md3                                 FB4_2             152  I/O       I
md4                                 FB11_9            92   I/O       I
md5                                 FB6_5             143  I/O       I
md6                                 FB6_3             142  I/O       I
md7                                 FB3_17            44   I/O       I
md8                                 FB11_12           95   I/O       I
md9                                 FB6_12            148  I/O       I
omni_d                              FB8_15            138  I/O       I
omni_e                              FB3_9             37   I/O       I
omni_f                              FB10_12           122  I/O       I
pause                               FB11_6            90   I/O       I
rev_req                             FB11_3            88   I/O       I
run                                 FB7_5             60   I/O       I
tp1                                 FB9_17            86   I/O       I
tp3                                 FB3_14            42   GCK/I/O   GCK
tp4                                 FB7_9             64   I/O       I
ts1                                 FB1_9             24   I/O       I
ts2                                 FB7_3             59   I/O       I
ts3                                 FB12_6            104  I/O       I
ts4                                 FB10_5            115  I/O       I
user_mode                           FB8_17            139  I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          13          31          31           48         0/11      12   
FB2          15          32          32           54         3/5       11   
FB3           4          34          34           29         1/3       11   
FB4          13          33          33           39         4/5       11   
FB5          11          31          31           48         2/8       11   
FB6          15          32          32           35         2/1       11   
FB7           4          33          33           27         2/2       11   
FB8          18          36          36           44         5/0       11   
FB9          14          35          35           53         5/0       11   
FB10         16          28          28           40         4/0       11   
FB11         13          31          31           36         5/0       11   
FB12         14          36          36           50         5/0       11   
            ----                                -----       -----     ----- 
            150                                  503        38/35     133   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB1_1               (b)     
ma0                   4       0     0   1     FB1_2   STD   18    I/O     I/O
ma10                  4       0     0   1     FB1_3   STD   19    I/O     I/O
(unused)              0       0     0   5     FB1_4               (b)     
ma11                  4       0     0   1     FB1_5   STD   21    I/O     I/O
ma1                   4       0     0   1     FB1_6   STD   22    I/O     I/O
(unused)              0       0     0   5     FB1_7               (b)     
ma2                   4       0     0   1     FB1_8   STD   23    I/O     I/O
(unused)              0       0     0   5     FB1_9         24    I/O     I
(unused)              0       0     0   5     FB1_10              (b)     
ma4                   4       0     0   1     FB1_11  STD   25    I/O     I/O
ma5                   4       0     0   1     FB1_12  STD   26    I/O     I/O
sw_momentary1_Q       2       0     0   3     FB1_13  STD         (b)     (b)
ma7                   4       0     0   1     FB1_14  STD   27    I/O     I/O
ma8                   4       0     0   1     FB1_15  STD   28    I/O     I/O
ma9                   4       0     0   1     FB1_16  STD   29    I/O     I/O
ma3                   4       0     0   1     FB1_17  STD   30    I/O     I/O
sw_halt_Q             2       0     0   3     FB1_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: bk_cycle          12: ma5.LFBK          22: pdata2.PIN       
  2: byte_cnt0_Q       13: ma6               23: pdata3.PIN       
  3: byte_cnt1_Q       14: ma7.LFBK          24: pdata4.PIN       
  4: data_mode_Q       15: ma8.LFBK          25: pdata6.PIN       
  5: ma0.LFBK          16: ma9.LFBK          26: pdata7.PIN       
  6: ma1.LFBK          17: ma_inc_Q          27: reg_num0_Q       
  7: ma10.LFBK         18: our_addr          28: reg_num1_Q       
  8: ma11.LFBK         19: par_rx_rising_Q   29: reg_num2_Q       
  9: ma2.LFBK          20: pdata0.PIN        30: sw_halt_Q.LFBK   
 10: ma3.LFBK          21: pdata1.PIN        31: sw_momentary1_Q.LFBK
 11: ma4.LFBK         

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ma0                  XXXXXXXXXXXXXXXXXXX...X...XXX........... 23      23
ma10                 XXXX..XX........XXX.X.....XXX........... 13      13
ma11                 XXXX...X........XXXX......XXX........... 12      12
ma1                  XXXX.XXXXXXXXXXXXXX..X....XXX........... 22      22
ma2                  XXXX..XXXXXXXXXXXXX.X.....XXX........... 21      21
ma4                  XXXX..XX..XXXXXXXXX......XXXX........... 19      19
ma5                  XXXX..XX...XXXXXXXX.....X.XXX........... 18      18
sw_momentary1_Q      .XXX.............XX.X.....XXX.X......... 10      10
ma7                  XXXX..XX.....XXXXXX....X..XXX........... 16      16
ma8                  XXXX..XX......XXXXX...X...XXX........... 15      15
ma9                  XXXX..XX.......XXXX..X....XXX........... 14      14
ma3                  XXXX..XX.XXXXXXXXXXX......XXX........... 20      20
sw_halt_Q            .XXX.............XX.....X.XXXX.......... 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               32/4
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB2_1               (b)     
(unused)              0       0   \/2   3     FB2_2         6     GTS/I/O (b)
periph_ack            8       3<-   0   0     FB2_3   STD   7     I/O     O
(unused)              0       0   /\1   4     FB2_4               (b)     (b)
par_rx_rising_Q       1       0     0   4     FB2_5   STD   8     GTS/I/O (b)
omni_data0            5       0     0   0     FB2_6   STD   9     I/O     I/O
host_clk_d2_Q         1       0     0   4     FB2_7   STD         (b)     (b)
omni_data5            5       0     0   0     FB2_8   STD   11    I/O     I/O
omni_data6            5       0     0   0     FB2_9   STD   12    I/O     I/O
sw_step_Q             2       0     0   3     FB2_10  STD         (b)     (b)
omni_data7            5       0     0   0     FB2_11  STD   13    I/O     I/O
omni_data8            5       0     0   0     FB2_12  STD   14    I/O     I/O
sw_start_Q            2       0     0   3     FB2_13  STD         (b)     (b)
our_addr              5       0     0   0     FB2_14  STD   15    I/O     O
sw_sw                 2       0     0   3     FB2_15  STD   16    I/O     O
data_mode_Q           2       0     0   3     FB2_16  STD         (b)     (b)
host_clk_cnt1_Q       3       0     0   2     FB2_17  STD   17    I/O     I
host_clk_cnt0_Q       3       0     0   2     FB2_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: ack_rev           12: omni_data5.LFBK   23: periph_ack.LFBK  
  2: byte_cnt0_Q       13: omni_data6.LFBK   24: reg_num0_Q       
  3: byte_cnt1_Q       14: omni_data7.LFBK   25: reg_num1_Q       
  4: data_mode_Q.LFBK  15: omni_data8.LFBK   26: reg_num2_Q       
  5: ecp_mode          16: omni_data_out_COM/omni_data_out_COM_D2__$INT 27: rev_req_cnt0     
  6: host_ack          17: our_addr.LFBK     28: rev_req_cnt1     
  7: host_clk_cnt0_Q.LFBK 18: par_rx_rising_Q.LFBK 29: sw_start_Q.LFBK  
  8: host_clk_cnt1_Q.LFBK 19: pdata3.PIN        30: sw_step_Q.LFBK   
  9: host_clk_d1_Q     20: pdata4.PIN        31: sw_sw.LFBK       
 10: host_clk_d2_Q.LFBK 21: pdata5.PIN        32: write_break_pending_Q
 11: omni_data0.LFBK   22: pdata6.PIN       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
periph_ack           X....XXX.X......X.XXXXXXXXXX...X........ 17      17
par_rx_rising_Q      ......XXXX............X................. 5       5
omni_data0           .XXX......X....XXXX....XXX.............. 11      11
host_clk_d2_Q        ........X............................... 1       1
omni_data5           .XXX.......X...XXX...X.XXX.............. 11      11
omni_data6           .XXX........X..XXX..X..XXX.............. 11      11
sw_step_Q            .XXX............XX..X..XXX...X.......... 10      10
omni_data7           .XXX.........X.XXX.X...XXX.............. 11      11
omni_data8           .XXX..........XXXXX....XXX.............. 11      11
sw_start_Q           .XXX............XX...X.XXX..X........... 10      10
our_addr             X...XX..........XXXXXX.................. 9       9
sw_sw                .XXX............XX.X...XXX....X......... 10      10
data_mode_Q          X...XX..........X.....X................. 5       5
host_clk_cnt1_Q      ......XXXX.............................. 4       4
host_clk_cnt0_Q      ......XXXX.............................. 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               34/2
Number of signals used by logic mapping into function block:  34
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0   \/3   2     FB3_1               (b)     (b)
pdata0               10       5<-   0   0     FB3_2   STD   32    I/O     I/O
(unused)              0       0   /\2   3     FB3_3         33    GCK/I/O GCK/I
(unused)              0       0     0   5     FB3_4               (b)     
(unused)              0       0     0   5     FB3_5         34    I/O     
(unused)              0       0     0   5     FB3_6         35    GCK/I/O GCK
(unused)              0       0   \/3   2     FB3_7               (b)     (b)
pdata1               10       5<-   0   0     FB3_8   STD   36    I/O     I/O
(unused)              0       0   /\2   3     FB3_9         37    I/O     I
(unused)              0       0   \/1   4     FB3_10              (b)     (b)
pdata4                7       2<-   0   0     FB3_11  STD   38    I/O     I/O
(unused)              0       0   /\1   4     FB3_12        39    I/O     (b)
(unused)              0       0     0   5     FB3_13              (b)     
(unused)              0       0     0   5     FB3_14        42    GCK/I/O GCK
test_reg0             2       0     0   3     FB3_15  STD   43    I/O     O
(unused)              0       0     0   5     FB3_16              (b)     
(unused)              0       0     0   5     FB3_17        44    I/O     I
(unused)              0       0     0   5     FB3_18              (b)     

Signals Used by Logic in Function Block
  1: ack_rev           13: disk_addr3_Q      24: ma3.PIN          
  2: byte_cnt0_Q       14: disk_addr7_Q      25: ma7.PIN          
  3: byte_cnt1_Q       15: ema2.PIN          26: our_addr         
  4: data_mode_Q       16: latch_led10_Q     27: par_rx_rising_Q  
  5: dbk_data10_Q      17: latch_led11_Q     28: pdata0.PIN       
  6: dbk_data11_Q      18: latch_led2_Q      29: reg_num0_Q       
  7: dbk_data2_Q       19: latch_led3_Q      30: reg_num1_Q       
  8: dbk_data3_Q       20: latch_led7_Q      31: reg_num2_Q       
  9: dbk_data7_Q       21: ma10.PIN          32: test_reg0.LFBK   
 10: disk_addr10_Q     22: ma11.PIN          33: test_reg1        
 11: disk_addr11_Q     23: ma2.PIN           34: test_reg4        
 12: disk_addr2_Q     

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
pdata0               XXX..X.X..X.X...X.X..X.X.X..XXXX........ 16      16
pdata1               XXX.X.X..X.X...X.X..X.X..X..XXX.X....... 16      16
pdata4               XXX.....X....XX....X....XX..XXX..X...... 13      13
test_reg0            .XXX.....................XXXXXXX........ 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               33/3
Number of signals used by logic mapping into function block:  33
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB4_1               (b)     
(unused)              0       0   \/1   4     FB4_2         152   I/O     I
pdata7                7       2<-   0   0     FB4_3   STD   153   I/O     I/O
(unused)              0       0   /\1   4     FB4_4               (b)     (b)
ema0                  3       0     0   2     FB4_5   STD   154   I/O     I/O
ema1                  3       0     0   2     FB4_6   STD   155   I/O     I/O
(unused)              0       0     0   5     FB4_7               (b)     
ema2                  3       0     0   2     FB4_8   STD   156   I/O     I/O
test_reg4             2       0     0   3     FB4_9   STD   158   I/O     O
(unused)              0       0     0   5     FB4_10              (b)     
dbk_data5_Q           2       0     0   3     FB4_11  STD   159   GSR/I/O GSR/I
test_reg5             2       0     0   3     FB4_12  STD   2     GTS/I/O O
dbk_data4_Q           2       0     0   3     FB4_13  STD         (b)     (b)
test_reg6             2       0     0   3     FB4_14  STD   3     I/O     O
test_reg7             2       0     0   3     FB4_15  STD   4     GTS/I/O O
byte_cnt1_Q           2       0   \/1   2     FB4_16  STD         (b)     (b)
pdata6                7       2<-   0   0     FB4_17  STD   5     I/O     I/O
byte_cnt0_Q           2       0   /\1   2     FB4_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: ack_rev           12: ema1.LFBK         23: pdata5.PIN       
  2: bk_cycle          13: ema2.LFBK         24: pdata6.PIN       
  3: byte_cnt0_Q.LFBK  14: latch_led4_Q      25: pdata7.PIN       
  4: byte_cnt1_Q.LFBK  15: latch_led5_Q      26: reg_num0_Q       
  5: data_mode_Q       16: ma4.PIN           27: reg_num1_Q       
  6: dbk_data4_Q.LFBK  17: ma5.PIN           28: reg_num2_Q       
  7: dbk_data5_Q.LFBK  18: md4               29: run              
  8: disk_addr4_Q      19: md5               30: test_reg4.LFBK   
  9: disk_addr5_Q      20: our_addr          31: test_reg5.LFBK   
 10: ema0.LFBK         21: par_rx_rising_Q   32: test_reg6.LFBK   
 11: ema0.PIN          22: pdata4.PIN        33: test_reg7.LFBK   

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
pdata7               X.XX.X.X.....X.X...X.....XXXX...X....... 13      13
ema0                 .XXXX....X.........XX..X.XXX............ 11      11
ema1                 .XXXX......X.......XX.X..XXX............ 11      11
ema2                 .XXXX.......X......XXX...XXX............ 11      11
test_reg4            ..XXX..............XXX...XXX.X.......... 10      10
dbk_data5_Q          .X....X...........X..................... 3       3
test_reg5            ..XXX..............XX.X..XXX..X......... 10      10
dbk_data4_Q          .X...X...........X...................... 3       3
test_reg6            ..XXX..............XX..X.XXX...X........ 10      10
test_reg7            ..XXX..............XX...XXXX....X....... 10      10
byte_cnt1_Q          ..XXX...............X................... 4       4
pdata6               X.XX..X.X.X...X.X..X.....XXX...X........ 13      13
byte_cnt0_Q          ..X.X...............X................... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0   \/2   3     FB5_1               (b)     (b)
pdata5                7       2<-   0   0     FB5_2   STD   45    I/O     I/O
omni_data10           5       0     0   0     FB5_3   STD   47    I/O     I/O
(unused)              0       0     0   5     FB5_4               (b)     
omni_data11           5       0     0   0     FB5_5   STD   48    I/O     I/O
omni_data1            5       0     0   0     FB5_6   STD   49    I/O     I/O
(unused)              0       0     0   5     FB5_7               (b)     
omni_data2            5       0     0   0     FB5_8   STD   50    I/O     I/O
omni_data3            5       0     0   0     FB5_9   STD   52    I/O     I/O
(unused)              0       0     0   5     FB5_10              (b)     
omni_data4            5       0     0   0     FB5_11  STD   53    I/O     I/O
omni_data9            5       0     0   0     FB5_12  STD   54    I/O     I/O
(unused)              0       0     0   5     FB5_13              (b)     
test_reg1             2       0     0   3     FB5_14  STD   55    I/O     O
test_reg3             2       0     0   3     FB5_15  STD   56    I/O     O
(unused)              0       0     0   5     FB5_16              (b)     
(unused)              0       0     0   5     FB5_17        57    I/O     I
sw_momentary0_Q       2       0     0   3     FB5_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: ack_rev           12: omni_data11.LFBK  22: pdata2.PIN       
  2: byte_cnt0_Q       13: omni_data2.LFBK   23: pdata3.PIN       
  3: byte_cnt1_Q       14: omni_data3.LFBK   24: pdata7.PIN       
  4: data_mode_Q       15: omni_data4.LFBK   25: reg_num0_Q       
  5: dbk_data6_Q       16: omni_data9.LFBK   26: reg_num1_Q       
  6: disk_addr6_Q      17: omni_data_out_COM/omni_data_out_COM_D2__$INT 27: reg_num2_Q       
  7: ema1.PIN          18: our_addr          28: sw_momentary0_Q.LFBK
  8: latch_led6_Q      19: par_rx_rising_Q   29: test_reg1.LFBK   
  9: ma6.PIN           20: pdata0.PIN        30: test_reg3.LFBK   
 10: omni_data1.LFBK   21: pdata1.PIN        31: test_reg5        
 11: omni_data10.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
pdata5               XXX.XXXXX........X......XXX...X......... 13      13
omni_data10          .XXX......X.....XXX.X...XXX............. 11      11
omni_data11          .XXX.......X....XXXX....XXX............. 11      11
omni_data1           .XXX.....X......XXX..X..XXX............. 11      11
omni_data2           .XXX........X...XXX.X...XXX............. 11      11
omni_data3           .XXX.........X..XXXX....XXX............. 11      11
omni_data4           .XXX..........X.XXX....XXXX............. 11      11
omni_data9           .XXX...........XXXX..X..XXX............. 11      11
test_reg1            .XXX.............XX.X...XXX.X........... 10      10
test_reg3            .XXX.............XX...X.XXX..X.......... 10      10
sw_momentary0_Q      .XXX.............XXX....XXXX............ 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining:               32/4
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB6_1               (b)     
ma6                   4       0     0   1     FB6_2   STD   140   I/O     I/O
(unused)              0       0     0   5     FB6_3         142   I/O     I
(unused)              0       0     0   5     FB6_4               (b)     
ma_inc_Q              1       0     0   4     FB6_5   STD   143   I/O     I
break_done_Q          1       0     0   4     FB6_6   STD   144   I/O     I
sw_rotary2_Q          2       0     0   3     FB6_7   STD         (b)     (b)
omni_data_in          2       0     0   3     FB6_8   STD   145   I/O     O
sw_rotary1_Q          2       0     0   3     FB6_9   STD   146   I/O     I
sw_rotary0_Q          2       0     0   3     FB6_10  STD         (b)     (b)
sw_momentary2_Q       2       0     0   3     FB6_11  STD   147   I/O     (b)
our_break_tp1_Q       2       0     0   3     FB6_12  STD   148   I/O     I
our_break_del_Q       2       0     0   3     FB6_13  STD         (b)     (b)
omni_data_out         2       0     0   3     FB6_14  STD   149   I/O     O
omni_data_out_COM/omni_data_out_COM_D2__$INT
                      2       0     0   3     FB6_15  STD   150   I/O     (b)
read_break_pending_Q
                      3       0     0   2     FB6_16  STD         (b)     (b)
need_break_Q          3       0     0   2     FB6_17  STD   151   I/O     (b)
latch_led9_Q/latch_led9_Q_CLKF
                      5       0     0   0     FB6_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: bk_cycle          12: ma9               23: reg_num0_Q       
  2: break_done_Q.LFBK 13: ma_inc_Q.LFBK     24: reg_num1_Q       
  3: byte_cnt0_Q       14: need_break_Q.LFBK 25: reg_num2_Q       
  4: byte_cnt1_Q       15: our_addr          26: sr_to_data       
  5: clk7d5            16: our_break_del_Q.LFBK 27: sw_momentary2_Q.LFBK
  6: data_mode_Q       17: par_rx_rising_Q   28: sw_rotary0_Q.LFBK
  7: ma10              18: pdata0.PIN        29: sw_rotary1_Q.LFBK
  8: ma11              19: pdata1.PIN        30: sw_rotary2_Q.LFBK
  9: ma6.LFBK          20: pdata2.PIN        31: tp1              
 10: ma7               21: pdata5.PIN        32: ts2              
 11: ma8               22: read_break_pending_Q.LFBK

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ma6                  X.XX.XXXXXXXX.X.X...X.XXX............... 17      17
ma_inc_Q             .X.............X........................ 2       2
break_done_Q         X..............X........................ 2       2
sw_rotary2_Q         ..XX.X........X.X..X..XXX....X.......... 10      10
omni_data_in         X.............X.......XXXX.....X........ 7       7
sw_rotary1_Q         ..XX.X........X.X.X...XXX...X........... 10      10
sw_rotary0_Q         ..XX.X........X.XX....XXX..X............ 10      10
sw_momentary2_Q      ..XX.X........X.X..X..XXX.X............. 10      10
our_break_tp1_Q      X.............................X......... 2       2
our_break_del_Q      XX.............X........................ 3       3
omni_data_out        X.............X.......XXXX.....X........ 7       7
omni_data_out_COM/omni_data_out_COM_D2__$INT 
                     X.............X.......XXXX.....X........ 7       7
read_break_pending_Q 
                     .XX..X.........XX....X.................. 6       6
need_break_Q         X.X..X.......XXXX....XXXX.....X......... 12      12
latch_led9_Q/latch_led9_Q_CLKF 
                     ....X......................XXXX......... 5       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB7 ***********************************
Number of function block inputs used/remaining:               33/3
Number of signals used by logic mapping into function block:  33
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0   \/3   2     FB7_1               (b)     (b)
pdata2               10       5<-   0   0     FB7_2   STD   58    I/O     I/O
(unused)              0       0   /\2   3     FB7_3         59    I/O     I
(unused)              0       0     0   5     FB7_4               (b)     
(unused)              0       0   \/3   2     FB7_5         60    I/O     I
pdata3               10       5<-   0   0     FB7_6   STD   62    I/O     I/O
(unused)              0       0   /\2   3     FB7_7               (b)     (b)
(unused)              0       0     0   5     FB7_8         63    I/O     I
(unused)              0       0     0   5     FB7_9         64    I/O     I
(unused)              0       0     0   5     FB7_10              (b)     
periph_clk            5       0     0   0     FB7_11  STD   65    I/O     O
(unused)              0       0     0   5     FB7_12        66    I/O     
(unused)              0       0     0   5     FB7_13              (b)     
(unused)              0       0     0   5     FB7_14        67    I/O     
test_reg2             2       0     0   3     FB7_15  STD   68    I/O     O
(unused)              0       0     0   5     FB7_16              (b)     
(unused)              0       0     0   5     FB7_17        69    I/O     
(unused)              0       0     0   5     FB7_18              (b)     

Signals Used by Logic in Function Block
  1: ack_rev           12: disk_addr9_Q      23: ma9.PIN          
  2: byte_cnt0_Q       13: host_clk_cnt0_Q   24: our_addr         
  3: byte_cnt1_Q       14: host_clk_cnt1_Q   25: par_rx_rising_Q  
  4: data_mode_Q       15: host_clk_d2_Q     26: pdata2.PIN       
  5: dbk_data0_Q       16: latch_led0_Q      27: periph_clk.LFBK  
  6: dbk_data1_Q       17: latch_led1_Q      28: read_break_pending_Q
  7: dbk_data8_Q       18: latch_led8_Q      29: reg_num0_Q       
  8: dbk_data9_Q       19: latch_led9_Q      30: reg_num1_Q       
  9: disk_addr0_Q      20: ma0.PIN           31: reg_num2_Q       
 10: disk_addr1_Q      21: ma1.PIN           32: test_reg2.LFBK   
 11: disk_addr8_Q      22: ma8.PIN           33: test_reg3        

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
pdata2               XXX..X.X.X.X....X.X.X.XX....XXXX........ 16      16
pdata3               XXX.X.X.X.X....X.X.X.X.X....XXX.X....... 16      16
periph_clk           X...........XXX........X..XXXXX......... 10      10
test_reg2            .XXX...................XXX..XXXX........ 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB8 ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
sw_start_d1_Q         2       0     0   3     FB8_1   STD         (b)     (b)
mem_start             2       0     0   3     FB8_2   STD   126   I/O     O
dbk_data9_Q           2       0     0   3     FB8_3   STD   128   I/O     (b)
dbk_data8_Q           2       0     0   3     FB8_4   STD         (b)     (b)
bk_data_cont          1       0     0   4     FB8_5   STD   129   I/O     O
dbk_data7_Q           2       0     0   3     FB8_6   STD   130   I/O     (b)
dbk_data6_Q           2       0     0   3     FB8_7   STD         (b)     (b)
init_out              1       0     0   4     FB8_8   STD   131   I/O     O
dbk_data3_Q           2       0     0   3     FB8_9   STD   132   I/O     (b)
dbk_data10_Q          2       0     0   3     FB8_10  STD         (b)     (b)
load_addr             1       0     0   4     FB8_11  STD   133   I/O     O
sw_cycle_Q            4       0     0   1     FB8_12  STD   134   I/O     I
disk_addr9_Q          4       0     0   1     FB8_13  STD         (b)     (b)
load_addr_en          1       0     0   4     FB8_14  STD   135   I/O     O
disk_addr2_Q          4       0     0   1     FB8_15  STD   138   I/O     I
disk_addr1_Q          4       0     0   1     FB8_16  STD         (b)     (b)
disk_addr11_Q         4       0     0   1     FB8_17  STD   139   I/O     I
disk_addr10_Q         4       0     0   1     FB8_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: bk_cycle          13: md10              25: omni_data2.PIN   
  2: dbk_data10_Q.LFBK 14: md11              26: omni_data9.PIN   
  3: dbk_data3_Q.LFBK  15: md3               27: pause            
  4: dbk_data6_Q.LFBK  16: md4               28: run              
  5: dbk_data7_Q.LFBK  17: md5               29: sw_cycle_Q.LFBK  
  6: dbk_data8_Q.LFBK  18: md6               30: sw_momentary0_Q  
  7: dbk_data9_Q.LFBK  19: md7               31: sw_momentary1_Q  
  8: disk_addr10_Q.LFBK 20: md8               32: sw_momentary2_Q  
  9: disk_addr11_Q.LFBK 21: md9               33: sw_pulse_Q       
 10: disk_addr1_Q.LFBK 22: omni_data0.PIN    34: sw_start_Q       
 11: disk_addr2_Q.LFBK 23: omni_data1.PIN    35: sw_start_d2_Q    
 12: disk_addr9_Q.LFBK 24: omni_data10.PIN   36: ts1              

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
sw_start_d1_Q        ..............................XX.X...... 3       3
mem_start            .............................XXXX....... 4       4
dbk_data9_Q          X.....X.............X................... 3       3
dbk_data8_Q          X....X.............X.................... 3       3
bk_data_cont         ............................XXXX........ 4       4
dbk_data7_Q          X...X.............X..................... 3       3
dbk_data6_Q          X..X.............X...................... 3       3
init_out             .............................XXXX....... 4       4
dbk_data3_Q          X.X...........X......................... 3       3
dbk_data10_Q         XX..........X........................... 3       3
load_addr            ..............................XXX....... 3       3
sw_cycle_Q           ...........................X..XX.XXX.... 6       6
disk_addr9_Q         ...........XXXXXXXXXX...X.X............. 12      12
load_addr_en         ............................X.XX........ 3       3
disk_addr2_Q         ..........X.XXXXXXXXX....XX............. 12      12
disk_addr1_Q         .........X..XXXXXXXXX..X..X............. 12      12
disk_addr11_Q        ........X...XXXXXXXXXX....X............. 12      12
disk_addr10_Q        .......X....XXXXXXXXX.X...X............. 12      12
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB9 ***********************************
Number of function block inputs used/remaining:               35/1
Number of signals used by logic mapping into function block:  35
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
latch_led0_Q          6       3<- /\2   0     FB9_1   STD         (b)     (b)
ma_ms_load            2       0   /\3   0     FB9_2   STD   72    I/O     O
(unused)              0       0     0   5     FB9_3         74    I/O     
(unused)              0       0     0   5     FB9_4               (b)     
bk_cycle              2       0     0   3     FB9_5   STD   76    I/O     O
(unused)              0       0     0   5     FB9_6         77    I/O     I
cpma_disable_COM/cpma_disable_COM_SETF__$INT
                      1       0     0   4     FB9_7   STD         (b)     (b)
our_break             2       0     0   3     FB9_8   STD   78    I/O     O
dbk_data2_Q           2       0   \/1   2     FB9_9   STD   79    I/O     I
latch_led8_Q          6       1<-   0   0     FB9_10  STD         (b)     (b)
break_prio            1       0   \/1   3     FB9_11  STD   82    I/O     O
latch_led6_Q          6       1<-   0   0     FB9_12  STD   83    I/O     (b)
latch_led2_Q          6       1<-   0   0     FB9_13  STD         (b)     (b)
md_dir                1       0   /\1   3     FB9_14  STD   84    I/O     O
latch_led1_Q          6       1<-   0   0     FB9_15  STD   85    I/O     (b)
(unused)              0       0   /\1   4     FB9_16              (b)     (b)
latch_led11_Q         6       1<-   0   0     FB9_17  STD   86    I/O     I
latch_led10_Q         6       2<- /\1   0     FB9_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: bk_cycle.LFBK     13: omni_d            25: reg_num0_Q       
  2: bk_in_prog        14: omni_data0.PIN    26: reg_num1_Q       
  3: dbk_data2_Q.LFBK  15: omni_data1.PIN    27: reg_num2_Q       
  4: initialize        16: omni_data10.PIN   28: sw_rotary0_Q     
  5: latch_led9_Q/latch_led9_Q_CLKF 17: omni_data11.PIN   29: sw_rotary1_Q     
  6: md0               18: omni_data2.PIN    30: sw_rotary2_Q     
  7: md1               19: omni_data6.PIN    31: sw_sw            
  8: md10              20: omni_data8.PIN    32: tp1              
  9: md11              21: omni_e            33: tp4              
 10: md2               22: omni_f            34: ts1              
 11: md6               23: our_addr          35: ts4              
 12: md8               24: our_break_tp1_Q  

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
latch_led0_Q         ....XX.......X.......X.....XXX...X...... 8       8
ma_ms_load           X..............................X........ 2       2
bk_cycle             .X...........XX..X..............X....... 5       5
cpma_disable_COM/cpma_disable_COM_SETF__$INT 
                     ...X...........................X........ 2       2
our_break            .X...........XX..X..............X....... 5       5
dbk_data2_Q          X.X......X.............................. 3       3
latch_led8_Q         ....X......X.......X.......XXXX..X...... 8       8
break_prio           .X................................X..... 2       2
latch_led6_Q         X...X.....X.......X...XXXXXXXX...X...... 13      13
latch_led2_Q         ....X....X.......X..X......XXX...X...... 8       8
md_dir               X.....................XXXXX............. 6       6
latch_led1_Q         ....X.X.....X.X............XXX...X...... 8       8
latch_led11_Q        X...X...X.......X..........XXX...X...... 8       8
latch_led10_Q        .X..X..X.......X...........XXX...X...... 8       8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB10 ***********************************
Number of function block inputs used/remaining:               28/8
Number of signals used by logic mapping into function block:  28
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB10_1              (b)     
ack_rev               3       0     0   2     FB10_2  STD   113   I/O     O
(unused)              0       0     0   5     FB10_3        114   I/O     
write_break_pending_Q
                      2       0     0   3     FB10_4  STD         (b)     (b)
reg_num2_Q            2       0     0   3     FB10_5  STD   115   I/O     I
ma_in                 2       0     0   3     FB10_6  STD   116   I/O     O
reg_num1_Q            2       0     0   3     FB10_7  STD         (b)     (b)
reg_num0_Q            2       0     0   3     FB10_8  STD   117   I/O     I
host_clk_d1_Q         2       0     0   3     FB10_9  STD   118   I/O     (b)
delay_cnt5_Q          2       0     0   3     FB10_10 STD         (b)     (b)
rev_req_cnt0          2       0     0   3     FB10_11 STD   119   I/O     O
delay_cnt0_Q          2       0     0   3     FB10_12 STD   122   I/O     I
sw_pulse_Q            3       0     0   2     FB10_13 STD         (b)     (b)
delay_cnt4_Q          3       0     0   2     FB10_14 STD   123   I/O     (b)
rev_req_cnt1          2       0     0   3     FB10_15 STD   124   I/O     O
delay_cnt1_Q          3       0     0   2     FB10_16 STD         (b)     (b)
delay_cnt3_Q          4       0     0   1     FB10_17 STD   125   I/O     (b)
delay_cnt2_Q          4       0     0   1     FB10_18 STD         (b)     (b)

Signals Used by Logic in Function Block
  1: ack_rev.LFBK      11: delay_cnt5_Q.LFBK 20: reg_num0_Q.LFBK  
  2: break_done_Q      12: ecp_mode          21: reg_num1_Q.LFBK  
  3: byte_cnt0_Q       13: host_ack          22: reg_num2_Q.LFBK  
  4: byte_cnt1_Q       14: host_clk          23: rev_req_cnt0.LFBK
  5: data_mode_Q       15: our_addr          24: rev_req_cnt1.LFBK
  6: delay_cnt0_Q.LFBK 16: par_rx_rising_Q   25: rev_req_sync     
  7: delay_cnt1_Q.LFBK 17: pdata0.PIN        26: sw_pulse_Q.LFBK  
  8: delay_cnt2_Q.LFBK 18: pdata1.PIN        27: sw_start_d1_Q    
  9: delay_cnt3_Q.LFBK 19: pdata2.PIN        28: write_break_pending_Q.LFBK
 10: delay_cnt4_Q.LFBK

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ack_rev              X.............X....XXXXX................ 7       7
write_break_pending_Q 
                     .XX.X.........XX...XXX.....X............ 9       9
reg_num2_Q           X..........XX..X..X..X.................. 6       6
ma_in                ..XX..........X....XXX.................. 6       6
reg_num1_Q           X..........XX..X.X..X................... 6       6
reg_num0_Q           X..........XX..XX..X.................... 6       6
host_clk_d1_Q        X...........XX.......................... 3       3
delay_cnt5_Q         .....XXXXXX...............X............. 7       7
rev_req_cnt0         ......................XXX............... 3       3
delay_cnt0_Q         .....XXXXXX...............X............. 7       7
sw_pulse_Q           .....XXXXXX..............XX............. 8       8
delay_cnt4_Q         .....XXXXXX...............X............. 7       7
rev_req_cnt1         ......................XXX............... 3       3
delay_cnt1_Q         .....XXXXXX...............X............. 7       7
delay_cnt3_Q         .....XXXXXX...............X............. 7       7
delay_cnt2_Q         .....XXXXXX...............X............. 7       7
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB11 ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB11_1              (b)     
bk_in_prog            2       0     0   3     FB11_2  STD   87    I/O     O
(unused)              0       0     0   5     FB11_3        88    I/O     I
(unused)              0       0     0   5     FB11_4              (b)     
cpma_disable          2       0     0   3     FB11_5  STD   89    I/O     O
(unused)              0       0     0   5     FB11_6        90    I/O     I
(unused)              0       0     0   5     FB11_7              (b)     
stop                  2       0     0   3     FB11_8  STD   91    I/O     O
sw_start_d2_Q         1       0     0   4     FB11_9  STD   92    I/O     I
disk_addr8_Q          4       0     0   1     FB11_10 STD         (b)     (b)
periph_req            0       0     0   5     FB11_11 STD   93    I/O     O
disk_addr7_Q          4       0     0   1     FB11_12 STD   95    I/O     I
disk_addr6_Q          4       0     0   1     FB11_13 STD         (b)     (b)
rev_req_sync          1       0     0   4     FB11_14 STD   96    I/O     O
disk_addr5_Q          4       0     0   1     FB11_15 STD   97    I/O     I
disk_addr4_Q          4       0     0   1     FB11_16 STD         (b)     (b)
disk_addr3_Q          4       0     0   1     FB11_17 STD   98    I/O     I
disk_addr0_Q          4       0     0   1     FB11_18 STD         (b)     (b)

Signals Used by Logic in Function Block
  1: cpma_disable_COM/cpma_disable_COM_SETF__$INT 12: md3               22: omni_data4.PIN   
  2: disk_addr0_Q.LFBK 13: md4               23: omni_data5.PIN   
  3: disk_addr3_Q.LFBK 14: md5               24: omni_data6.PIN   
  4: disk_addr4_Q.LFBK 15: md6               25: omni_data7.PIN   
  5: disk_addr5_Q.LFBK 16: md7               26: omni_data8.PIN   
  6: disk_addr6_Q.LFBK 17: md8               27: pause            
  7: disk_addr7_Q.LFBK 18: md9               28: rev_req          
  8: disk_addr8_Q.LFBK 19: need_break_Q      29: sw_halt_Q        
  9: fset              20: omni_data11.PIN   30: sw_start_d1_Q    
 10: md10              21: omni_data3.PIN    31: sw_step_Q        
 11: md11             

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
bk_in_prog           X.................X..................... 2       2
cpma_disable         X.................X..................... 2       2
stop                 ........X...................X.X......... 3       3
sw_start_d2_Q        .............................X.......... 1       1
disk_addr8_Q         .......X.XXXXXXXXX..X.....X............. 12      12
periph_req           ........................................ 0       0
disk_addr7_Q         ......X..XXXXXXXXX...X....X............. 12      12
disk_addr6_Q         .....X...XXXXXXXXX....X...X............. 12      12
rev_req_sync         ...........................X............ 1       1
disk_addr5_Q         ....X....XXXXXXXXX.....X..X............. 12      12
disk_addr4_Q         ...X.....XXXXXXXXX......X.X............. 12      12
disk_addr3_Q         ..X......XXXXXXXXX.......XX............. 12      12
disk_addr0_Q         .X.......XXXXXXXXX.X......X............. 12      12
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB12 ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
latch_led3_Q          6       2<- /\1   0     FB12_1  STD         (b)     (b)
ind1                  3       0   /\2   0     FB12_2  STD   101   I/O     O
(unused)              0       0     0   5     FB12_3        102   I/O     I
(unused)              0       0     0   5     FB12_4              (b)     
ind2                  3       0     0   2     FB12_5  STD   103   I/O     O
(unused)              0       0     0   5     FB12_6        104   I/O     I
dbk_data1_Q           2       0     0   3     FB12_7  STD         (b)     (b)
dbk_data11_Q          2       0     0   3     FB12_8  STD   105   I/O     (b)
key_cntrl             2       0     0   3     FB12_9  STD   106   I/O     O
dbk_data0_Q           2       0     0   3     FB12_10 STD         (b)     (b)
sr_to_data            3       0     0   2     FB12_11 STD   107   I/O     (b)
ms_ir_dis             2       0   \/1   2     FB12_12 STD   108   I/O     O
latch_led9_Q          6       1<-   0   0     FB12_13 STD         (b)     (b)
latch_led7_Q          6       1<-   0   0     FB12_14 STD   109   I/O     (b)
xflag                 1       0   /\1   3     FB12_15 STD   111   I/O     O
(unused)              0       0   \/1   4     FB12_16             (b)     (b)
latch_led5_Q          6       1<-   0   0     FB12_17 STD   112   I/O     (b)
latch_led4_Q          6       1<-   0   0     FB12_18 STD         (b)     (b)

Signals Used by Logic in Function Block
  1: bk_cycle          13: md2               25: pause            
  2: dbk_data0_Q.LFBK  14: md3               26: sw_cycle_Q       
  3: dbk_data11_Q.LFBK 15: md4               27: sw_momentary0_Q  
  4: dbk_data1_Q.LFBK  16: md5               28: sw_momentary1_Q  
  5: ecp_mode          17: md7               29: sw_momentary2_Q  
  6: ir0               18: md9               30: sw_rotary0_Q     
  7: ir1               19: omni_data3.PIN    31: sw_rotary1_Q     
  8: ir2               20: omni_data4.PIN    32: sw_rotary2_Q     
  9: latch_led9_Q/latch_led9_Q_CLKF 21: omni_data5.PIN    33: ts1              
 10: md0               22: omni_data7.PIN    34: ts2              
 11: md1               23: omni_data9.PIN    35: ts3              
 12: md11              24: omni_f            36: user_mode        

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
latch_led3_Q         .....X..X....X....X..........XXXX....... 8       8
ind1                 .........................X.XXXXX........ 6       6
ind2                 .........................X.XXX.X........ 5       5
dbk_data1_Q          X..X......X............................. 3       3
dbk_data11_Q         X.X........X............................ 3       3
key_cntrl            .........................XXXX........... 4       4
dbk_data0_Q          XX.......X.............................. 3       3
sr_to_data           .........XXXXX...X.....X.XXXX....XXX.... 14      14
ms_ir_dis            X........................X.X............ 3       3
latch_led9_Q         ........X........X....X.X....XXXX....... 8       8
latch_led7_Q         ........X.......X....X...XXXXXXXX....... 11      11
xflag                ....X................................... 1       1
latch_led5_Q         .......XX......X....X........XXXX....... 8       8
latch_led4_Q         ......X.X.....X....X.........XXXX....... 8       8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

 ema0.T  =  ema0.LFBK * pdata6.PIN * our_addr * byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q
       + /ema0.LFBK */pdata6.PIN * our_addr * byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q    
   ema0.CLKF =  clk7d5	;FCLK/GCK
   ema0.TRST = /bk_cycle
   ema0.PRLD =  GND


 ema1.T  =  ema1.LFBK * pdata5.PIN * our_addr * byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q
       + /ema1.LFBK */pdata5.PIN * our_addr * byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q    
   ema1.CLKF =  clk7d5	;FCLK/GCK
   ema1.TRST = /bk_cycle
   ema1.PRLD =  GND


 ema2.T  =  ema2.LFBK * pdata4.PIN * our_addr * byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q
       + /ema2.LFBK */pdata4.PIN * our_addr * byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q    
   ema2.CLKF =  clk7d5	;FCLK/GCK
   ema2.TRST = /bk_cycle
   ema2.PRLD =  GND


 ma0.T  =  ma0.LFBK * pdata3.PIN * our_addr * byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma0.LFBK */pdata3.PIN * our_addr * byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma10.LFBK */ma11.LFBK */ma1.LFBK */ma2.LFBK */ma3.LFBK
           */ma4.LFBK */ma5.LFBK */ma6 */ma7.LFBK */ma8.LFBK */ma9.LFBK
           * ma_inc_Q    
   ma0.CLKF =  clk7d5	;FCLK/GCK
   ma0.TRST = /bk_cycle
   ma0.PRLD =  GND


 ma10.T  = /ma11.LFBK * ma_inc_Q
       +  ma10.LFBK * pdata1.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma10.LFBK */pdata1.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q    
   ma10.CLKF =  clk7d5	;FCLK/GCK
   ma10.TRST = /bk_cycle
   ma10.PRLD =  GND


 ma11.T  =  ma_inc_Q
       +  ma11.LFBK * pdata0.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q * reg_num1_Q
           */reg_num2_Q
       + /ma11.LFBK */pdata0.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q * reg_num1_Q
           */reg_num2_Q    
   ma11.CLKF =  clk7d5	;FCLK/GCK
   ma11.TRST = /bk_cycle
   ma11.PRLD =  GND


 ma1.T  = /ma10.LFBK */ma11.LFBK */ma2.LFBK */ma3.LFBK */ma4.LFBK
           */ma5.LFBK */ma6 */ma7.LFBK */ma8.LFBK */ma9.LFBK * ma_inc_Q
       +  ma1.LFBK * pdata2.PIN * our_addr * byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma1.LFBK */pdata2.PIN * our_addr * byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q    
   ma1.CLKF =  clk7d5	;FCLK/GCK
   ma1.TRST = /bk_cycle
   ma1.PRLD =  GND


 ma2.T  = /ma10.LFBK */ma11.LFBK */ma3.LFBK */ma4.LFBK */ma5.LFBK
           */ma6 */ma7.LFBK */ma8.LFBK */ma9.LFBK * ma_inc_Q
       +  ma2.LFBK * pdata1.PIN * our_addr * byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma2.LFBK */pdata1.PIN * our_addr * byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q    
   ma2.CLKF =  clk7d5	;FCLK/GCK
   ma2.TRST = /bk_cycle
   ma2.PRLD =  GND


 ma3.T  = /ma10.LFBK */ma11.LFBK */ma4.LFBK */ma5.LFBK */ma6 */ma7.LFBK
           */ma8.LFBK */ma9.LFBK * ma_inc_Q
       +  ma3.LFBK * pdata0.PIN * our_addr * byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma3.LFBK */pdata0.PIN * our_addr * byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q    
   ma3.CLKF =  clk7d5	;FCLK/GCK
   ma3.TRST = /bk_cycle
   ma3.PRLD =  GND


 ma4.T  = /ma10.LFBK */ma11.LFBK */ma5.LFBK */ma6 */ma7.LFBK */ma8.LFBK
           */ma9.LFBK * ma_inc_Q
       +  ma4.LFBK * pdata7.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma4.LFBK */pdata7.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q    
   ma4.CLKF =  clk7d5	;FCLK/GCK
   ma4.TRST = /bk_cycle
   ma4.PRLD =  GND


 ma5.T  = /ma10.LFBK */ma11.LFBK */ma6 */ma7.LFBK */ma8.LFBK */ma9.LFBK
           * ma_inc_Q
       +  ma5.LFBK * pdata6.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma5.LFBK */pdata6.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q    
   ma5.CLKF =  clk7d5	;FCLK/GCK
   ma5.TRST = /bk_cycle
   ma5.PRLD =  GND


 ma6.T  = /ma10 */ma11 */ma7 */ma8 */ma9 * ma_inc_Q.LFBK
       +  ma6.LFBK * pdata5.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q.LFBK * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma6.LFBK */pdata5.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q.LFBK * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q    
   ma6.CLKF =  clk7d5	;FCLK/GCK
   ma6.TRST = /bk_cycle
   ma6.PRLD =  GND


 ma7.T  = /ma10.LFBK */ma11.LFBK */ma8.LFBK */ma9.LFBK * ma_inc_Q
       +  ma7.LFBK * pdata4.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma7.LFBK */pdata4.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q    
   ma7.CLKF =  clk7d5	;FCLK/GCK
   ma7.TRST = /bk_cycle
   ma7.PRLD =  GND


 ma8.T  = /ma10.LFBK */ma11.LFBK */ma9.LFBK * ma_inc_Q
       +  ma8.LFBK * pdata3.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma8.LFBK */pdata3.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q    
   ma8.CLKF =  clk7d5	;FCLK/GCK
   ma8.TRST = /bk_cycle
   ma8.PRLD =  GND


 ma9.T  = /ma10.LFBK */ma11.LFBK * ma_inc_Q
       +  ma9.LFBK * pdata2.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ma9.LFBK */pdata2.PIN * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q */ma_inc_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q    
   ma9.CLKF =  clk7d5	;FCLK/GCK
   ma9.TRST = /bk_cycle
   ma9.PRLD =  GND


 omni_data0.T  =  omni_data0.LFBK * pdata3.PIN * our_addr.LFBK * byte_cnt0_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK */reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       + /omni_data0.LFBK */pdata3.PIN * our_addr.LFBK * byte_cnt0_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK */reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       +  omni_data0.LFBK * pdata3.PIN * our_addr.LFBK * byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q
       + /omni_data0.LFBK */pdata3.PIN * our_addr.LFBK * byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q    
   omni_data0.CLKF =  clk7d5	;FCLK/GCK
   omni_data0.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data0.PRLD =  VCC


 omni_data10.T  =  omni_data10.LFBK * pdata1.PIN * our_addr */byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       + /omni_data10.LFBK */pdata1.PIN * our_addr */byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       +  omni_data10.LFBK * pdata1.PIN * our_addr */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q
       + /omni_data10.LFBK */pdata1.PIN * our_addr */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q    
   omni_data10.CLKF =  clk7d5	;FCLK/GCK
   omni_data10.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data10.PRLD =  VCC


 omni_data11.T  =  omni_data11.LFBK * pdata0.PIN * our_addr */byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       + /omni_data11.LFBK */pdata0.PIN * our_addr */byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       +  omni_data11.LFBK * pdata0.PIN * our_addr */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q
       + /omni_data11.LFBK */pdata0.PIN * our_addr */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q    
   omni_data11.CLKF =  clk7d5	;FCLK/GCK
   omni_data11.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data11.PRLD =  VCC


 omni_data1.T  =  omni_data1.LFBK * pdata2.PIN * our_addr * byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       + /omni_data1.LFBK */pdata2.PIN * our_addr * byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       +  omni_data1.LFBK * pdata2.PIN * our_addr * byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q
       + /omni_data1.LFBK */pdata2.PIN * our_addr * byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q    
   omni_data1.CLKF =  clk7d5	;FCLK/GCK
   omni_data1.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data1.PRLD =  VCC


 omni_data2.T  =  omni_data2.LFBK * pdata1.PIN * our_addr * byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       + /omni_data2.LFBK */pdata1.PIN * our_addr * byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       +  omni_data2.LFBK * pdata1.PIN * our_addr * byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q
       + /omni_data2.LFBK */pdata1.PIN * our_addr * byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q    
   omni_data2.CLKF =  clk7d5	;FCLK/GCK
   omni_data2.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data2.PRLD =  VCC


 omni_data3.T  =  omni_data3.LFBK * pdata0.PIN * our_addr * byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       + /omni_data3.LFBK */pdata0.PIN * our_addr * byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       +  omni_data3.LFBK * pdata0.PIN * our_addr * byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q
       + /omni_data3.LFBK */pdata0.PIN * our_addr * byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q    
   omni_data3.CLKF =  clk7d5	;FCLK/GCK
   omni_data3.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data3.PRLD =  VCC


 omni_data4.T  =  omni_data4.LFBK * pdata7.PIN * our_addr */byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       + /omni_data4.LFBK */pdata7.PIN * our_addr */byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       +  omni_data4.LFBK * pdata7.PIN * our_addr */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q
       + /omni_data4.LFBK */pdata7.PIN * our_addr */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q    
   omni_data4.CLKF =  clk7d5	;FCLK/GCK
   omni_data4.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data4.PRLD =  VCC


 omni_data5.T  =  omni_data5.LFBK * pdata6.PIN * our_addr.LFBK */byte_cnt0_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK */reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       + /omni_data5.LFBK */pdata6.PIN * our_addr.LFBK */byte_cnt0_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK */reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       +  omni_data5.LFBK * pdata6.PIN * our_addr.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q
       + /omni_data5.LFBK */pdata6.PIN * our_addr.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q    
   omni_data5.CLKF =  clk7d5	;FCLK/GCK
   omni_data5.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data5.PRLD =  VCC


 omni_data6.T  =  omni_data6.LFBK * pdata5.PIN * our_addr.LFBK */byte_cnt0_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK */reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       + /omni_data6.LFBK */pdata5.PIN * our_addr.LFBK */byte_cnt0_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK */reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       +  omni_data6.LFBK * pdata5.PIN * our_addr.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q
       + /omni_data6.LFBK */pdata5.PIN * our_addr.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q    
   omni_data6.CLKF =  clk7d5	;FCLK/GCK
   omni_data6.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data6.PRLD =  VCC


 omni_data7.T  =  omni_data7.LFBK * pdata4.PIN * our_addr.LFBK */byte_cnt0_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK */reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       + /omni_data7.LFBK */pdata4.PIN * our_addr.LFBK */byte_cnt0_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK */reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       +  omni_data7.LFBK * pdata4.PIN * our_addr.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q
       + /omni_data7.LFBK */pdata4.PIN * our_addr.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q    
   omni_data7.CLKF =  clk7d5	;FCLK/GCK
   omni_data7.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data7.PRLD =  VCC


 omni_data8.T  =  omni_data8.LFBK * pdata3.PIN * our_addr.LFBK */byte_cnt0_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK */reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       + /omni_data8.LFBK */pdata3.PIN * our_addr.LFBK */byte_cnt0_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK */reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       +  omni_data8.LFBK * pdata3.PIN * our_addr.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q
       + /omni_data8.LFBK */pdata3.PIN * our_addr.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q    
   omni_data8.CLKF =  clk7d5	;FCLK/GCK
   omni_data8.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data8.PRLD =  VCC


 omni_data9.T  =  omni_data9.LFBK * pdata2.PIN * our_addr */byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       + /omni_data9.LFBK */pdata2.PIN * our_addr */byte_cnt0_Q
           * data_mode_Q * par_rx_rising_Q */reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       +  omni_data9.LFBK * pdata2.PIN * our_addr */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q
       + /omni_data9.LFBK */pdata2.PIN * our_addr */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           */reg_num1_Q */reg_num2_Q    
   omni_data9.CLKF =  clk7d5	;FCLK/GCK
   omni_data9.TRST =  "omni_data_out_COM/omni_data_out_COM_D2__$INT"
   omni_data9.PRLD =  VCC


 pdata0  =  our_addr * test_reg0.LFBK * byte_cnt0_Q * reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       +  our_addr * byte_cnt0_Q * disk_addr3_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       +  our_addr * byte_cnt0_Q * dbk_data11_Q */reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       +  our_addr */byte_cnt0_Q * dbk_data3_Q */reg_num0_Q * reg_num1_Q
           */reg_num2_Q    
;Imported pterms
       + /ma11.PIN * our_addr * byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q
       +  our_addr * byte_cnt0_Q */byte_cnt1_Q * latch_led11_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q
       +  our_addr */byte_cnt0_Q * byte_cnt1_Q * disk_addr11_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q    
;Imported pterms
       + /ma3.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q
       +  our_addr */byte_cnt0_Q */byte_cnt1_Q * latch_led3_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q    
   pdata0.TRST = /ack_rev

 pdata1  =  our_addr * test_reg1 * byte_cnt0_Q * reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       +  our_addr * byte_cnt0_Q * disk_addr2_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       +  our_addr * byte_cnt0_Q * dbk_data10_Q */reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       +  our_addr */byte_cnt0_Q * dbk_data2_Q */reg_num0_Q * reg_num1_Q
           */reg_num2_Q    
;Imported pterms
       + /ma2.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q
       +  our_addr * byte_cnt0_Q */byte_cnt1_Q * latch_led10_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q
       +  our_addr */byte_cnt0_Q */byte_cnt1_Q * latch_led2_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q    
;Imported pterms
       + /ma10.PIN * our_addr * byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q
       +  our_addr */byte_cnt0_Q * byte_cnt1_Q * disk_addr10_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q    
   pdata1.TRST = /ack_rev

 pdata2  =  our_addr * test_reg2.LFBK * byte_cnt0_Q * reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       +  our_addr * byte_cnt0_Q * disk_addr1_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       +  our_addr * byte_cnt0_Q * dbk_data9_Q */reg_num0_Q * reg_num1_Q
           */reg_num2_Q
       +  our_addr */byte_cnt0_Q * dbk_data1_Q */reg_num0_Q * reg_num1_Q
           */reg_num2_Q    
;Imported pterms
       + /ma1.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q
       +  our_addr * byte_cnt0_Q */byte_cnt1_Q * latch_led9_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q
       +  our_addr */byte_cnt0_Q */byte_cnt1_Q * latch_led1_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q    
;Imported pterms
       + /ma9.PIN * our_addr * byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q
       +  our_addr */byte_cnt0_Q * byte_cnt1_Q * disk_addr9_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q    
   pdata2.TRST = /ack_rev

 pdata3  =  our_addr * test_reg3 * byte_cnt0_Q * reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       +  our_addr * byte_cnt0_Q * disk_addr0_Q * reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       +  our_addr * byte_cnt0_Q * dbk_data8_Q */reg_num0_Q * reg_num1_Q
           */reg_num2_Q
       +  our_addr */byte_cnt0_Q * dbk_data0_Q */reg_num0_Q * reg_num1_Q
           */reg_num2_Q    
;Imported pterms
       + /ma8.PIN * our_addr * byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q
       +  our_addr * byte_cnt0_Q */byte_cnt1_Q * latch_led8_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q
       +  our_addr */byte_cnt0_Q * byte_cnt1_Q * disk_addr8_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q    
;Imported pterms
       + /ma0.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q
       +  our_addr */byte_cnt0_Q */byte_cnt1_Q * latch_led0_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q    
   pdata3.TRST = /ack_rev

 pdata4  =  our_addr * test_reg4 * byte_cnt0_Q * reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       +  our_addr * byte_cnt0_Q * dbk_data7_Q */reg_num0_Q * reg_num1_Q
           */reg_num2_Q
       + /ma7.PIN * our_addr * byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q
       +  our_addr * byte_cnt0_Q */byte_cnt1_Q * latch_led7_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q    
;Imported pterms
       +  our_addr */byte_cnt0_Q * byte_cnt1_Q * disk_addr7_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q    
;Imported pterms
       + /ema2.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q    
   pdata4.TRST = /ack_rev

 pdata5  =  our_addr * test_reg5 * byte_cnt0_Q * reg_num0_Q * reg_num1_Q
           * reg_num2_Q
       +  our_addr * byte_cnt0_Q * dbk_data6_Q */reg_num0_Q * reg_num1_Q
           */reg_num2_Q
       + /ema1.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q
       +  our_addr */byte_cnt0_Q * byte_cnt1_Q * disk_addr6_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q    
;Imported pterms
       + /ma6.PIN * our_addr * byte_cnt0_Q * byte_cnt1_Q */reg_num0_Q
           */reg_num1_Q * reg_num2_Q
       +  our_addr * byte_cnt0_Q */byte_cnt1_Q * latch_led6_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q    
   pdata5.TRST = /ack_rev

 pdata6  =  our_addr * test_reg6.LFBK * byte_cnt0_Q.LFBK * reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       +  our_addr * byte_cnt0_Q.LFBK * dbk_data5_Q.LFBK */reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /ema0.PIN * our_addr */byte_cnt0_Q.LFBK * byte_cnt1_Q.LFBK
           */reg_num0_Q */reg_num1_Q * reg_num2_Q
       +  our_addr */byte_cnt0_Q.LFBK * byte_cnt1_Q.LFBK * disk_addr5_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q    
;Imported pterms
       +  our_addr * byte_cnt0_Q.LFBK */byte_cnt1_Q.LFBK * latch_led5_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q
;Imported pterms
       + /ma5.PIN * our_addr * byte_cnt0_Q.LFBK * byte_cnt1_Q.LFBK
           */reg_num0_Q */reg_num1_Q * reg_num2_Q
   pdata6.TRST = /ack_rev

 pdata7  =  our_addr * test_reg7.LFBK * byte_cnt0_Q.LFBK * reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       +  our_addr * byte_cnt0_Q.LFBK * dbk_data4_Q.LFBK */reg_num0_Q
           * reg_num1_Q */reg_num2_Q
       + /run * our_addr */byte_cnt0_Q.LFBK */byte_cnt1_Q.LFBK
           */reg_num0_Q */reg_num1_Q * reg_num2_Q
       +  our_addr */byte_cnt0_Q.LFBK * byte_cnt1_Q.LFBK * disk_addr4_Q
           * reg_num0_Q * reg_num1_Q */reg_num2_Q    
;Imported pterms
       + /ma4.PIN * our_addr * byte_cnt0_Q.LFBK * byte_cnt1_Q.LFBK
           */reg_num0_Q */reg_num1_Q * reg_num2_Q    
;Imported pterms
       +  our_addr * byte_cnt0_Q.LFBK */byte_cnt1_Q.LFBK * latch_led4_Q
           */reg_num0_Q */reg_num1_Q * reg_num2_Q    
   pdata7.TRST = /ack_rev

 ack_rev.T  = /ack_rev.LFBK */rev_req_cnt0.LFBK */rev_req_cnt1.LFBK
       +  ack_rev.LFBK * our_addr * rev_req_cnt0.LFBK * rev_req_cnt1.LFBK
           */reg_num0_Q.LFBK */reg_num1_Q.LFBK * reg_num2_Q.LFBK
       +  ack_rev.LFBK * our_addr * rev_req_cnt0.LFBK * rev_req_cnt1.LFBK
           */reg_num0_Q.LFBK * reg_num1_Q.LFBK */reg_num2_Q.LFBK    
   ack_rev.CLKF =  clk7d5	;FCLK/GCK
   ack_rev.PRLD =  GND


 bk_cycle :=  omni_data0.PIN * omni_data1.PIN * omni_data2.PIN */bk_in_prog    
   bk_cycle.CLKF =  tp4
   bk_cycle.RSTF =  initialize	;GSR
   bk_cycle.PRLD =  GND


/bk_data_cont  =  sw_cycle_Q.LFBK */sw_momentary0_Q */sw_momentary1_Q
           * sw_momentary2_Q    

 bk_in_prog := /need_break_Q    
   bk_in_prog.CLKF =  int_strobe	;FCLK/GCK
   bk_in_prog.SETF = /"cpma_disable_COM/cpma_disable_COM_SETF__$INT"
   bk_in_prog.PRLD =  VCC


 break_prio  = /ts4 */bk_in_prog    

 cpma_disable := /need_break_Q    
   cpma_disable.CLKF =  int_strobe	;FCLK/GCK
   cpma_disable.SETF = /"cpma_disable_COM/cpma_disable_COM_SETF__$INT"
   cpma_disable.PRLD =  VCC


/ind1  =  sw_cycle_Q */sw_momentary1_Q */sw_momentary2_Q
       +  sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q    

/ind2  = /sw_cycle_Q * sw_rotary0_Q */sw_rotary2_Q
       +  sw_momentary1_Q * sw_rotary0_Q */sw_rotary2_Q
       +  sw_momentary2_Q * sw_rotary0_Q */sw_rotary2_Q    

 init_out  = /sw_momentary0_Q * sw_momentary1_Q */sw_momentary2_Q
           * sw_pulse_Q    

/key_cntrl  =  sw_cycle_Q */sw_momentary1_Q * sw_momentary2_Q
       +  sw_cycle_Q * sw_momentary0_Q */sw_momentary1_Q    

 load_addr  = /sw_momentary1_Q */sw_momentary2_Q * sw_pulse_Q    

/load_addr_en  =  sw_cycle_Q.LFBK */sw_momentary1_Q */sw_momentary2_Q    

/ma_in  =  our_addr * byte_cnt0_Q */reg_num0_Q.LFBK */reg_num1_Q.LFBK
           * reg_num2_Q.LFBK
       +  our_addr * byte_cnt1_Q */reg_num0_Q.LFBK */reg_num1_Q.LFBK
           * reg_num2_Q.LFBK    

 ma_ms_load := /bk_cycle.LFBK    
   ma_ms_load.CLKF =  tp1
   ma_ms_load.RSTF =  initialize	;GSR
   ma_ms_load.PRLD =  GND


/md_dir  = /bk_cycle.LFBK * our_addr * our_break_tp1_Q */reg_num0_Q
           * reg_num1_Q * reg_num2_Q    

/mem_start  = /sw_momentary1_Q * sw_momentary2_Q * sw_pulse_Q
       +  sw_momentary0_Q * sw_momentary1_Q */sw_momentary2_Q
           * sw_pulse_Q    

/ms_ir_dis  = /bk_cycle
       +  sw_cycle_Q */sw_momentary1_Q    

 omni_data_in  =  sr_to_data
       + /ts2 */bk_cycle * our_addr */reg_num0_Q * reg_num1_Q
           * reg_num2_Q    

/omni_data_out  =  sr_to_data
       + /ts2 */bk_cycle * our_addr */reg_num0_Q * reg_num1_Q
           * reg_num2_Q    

 our_addr.T  =  ecp_mode */host_ack * pdata3.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q.LFBK
       +  ecp_mode */host_ack */pdata4.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q.LFBK
       +  ecp_mode */host_ack * pdata5.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q.LFBK
       +  ecp_mode */host_ack * pdata6.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q.LFBK
       +  ecp_mode */host_ack */pdata3.PIN * pdata4.PIN */pdata5.PIN
           */pdata6.PIN * ack_rev */our_addr.LFBK * par_rx_rising_Q.LFBK    
   our_addr.CLKF =  clk7d5	;FCLK/GCK
   our_addr.PRLD =  GND


 our_break :=  omni_data0.PIN * omni_data1.PIN * omni_data2.PIN */bk_in_prog    
   our_break.CLKF =  tp4
   our_break.RSTF =  initialize	;GSR
   our_break.PRLD =  GND


 periph_ack.T  = /ack_rev */periph_ack.LFBK
       + /ack_rev */rev_req_cnt0 */rev_req_cnt1
       +  ack_rev * periph_ack.LFBK * host_clk_cnt0_Q.LFBK * host_clk_cnt1_Q.LFBK
           * host_clk_d2_Q.LFBK
       +  our_addr.LFBK */periph_ack.LFBK * host_clk_cnt0_Q.LFBK
           * host_clk_cnt1_Q.LFBK */host_clk_d2_Q.LFBK * reg_num0_Q
       +  our_addr.LFBK */periph_ack.LFBK * host_clk_cnt0_Q.LFBK
           * host_clk_cnt1_Q.LFBK */host_clk_d2_Q.LFBK */write_break_pending_Q    
;Imported pterms
       +  our_addr.LFBK */periph_ack.LFBK * host_clk_cnt0_Q.LFBK
           * host_clk_cnt1_Q.LFBK */host_clk_d2_Q.LFBK */reg_num2_Q
       +  our_addr.LFBK */periph_ack.LFBK * host_clk_cnt0_Q.LFBK
           * host_clk_cnt1_Q.LFBK */host_clk_d2_Q.LFBK */reg_num1_Q    
;Imported pterms
       + /host_ack */pdata3.PIN * pdata4.PIN */pdata5.PIN */pdata6.PIN
           */periph_ack.LFBK * host_clk_cnt0_Q.LFBK * host_clk_cnt1_Q.LFBK
           */host_clk_d2_Q.LFBK    
   periph_ack.CLKF =  clk7d5	;FCLK/GCK
   periph_ack.PRLD =  GND


 periph_clk :=  ack_rev
       +  periph_clk.LFBK */host_clk_cnt0_Q
       +  periph_clk.LFBK */host_clk_cnt1_Q
       +  host_clk_cnt0_Q * host_clk_cnt1_Q */host_clk_d2_Q
       +  our_addr * periph_clk.LFBK */read_break_pending_Q */reg_num0_Q
           * reg_num1_Q */reg_num2_Q    
   periph_clk.CLKF =  clk7d5	;FCLK/GCK
   periph_clk.PRLD =  GND


 periph_req  = Vcc    

/rev_req_cnt0.T  =  rev_req_cnt0.LFBK * rev_req_cnt1.LFBK * rev_req_sync
       + /rev_req_cnt0.LFBK */rev_req_cnt1.LFBK */rev_req_sync    
   rev_req_cnt0.CLKF =  clk7d5	;FCLK/GCK
   rev_req_cnt0.PRLD =  GND


 rev_req_cnt1.T  =  rev_req_cnt0.LFBK */rev_req_cnt1.LFBK * rev_req_sync
       + /rev_req_cnt0.LFBK * rev_req_cnt1.LFBK */rev_req_sync    
   rev_req_cnt1.CLKF =  clk7d5	;FCLK/GCK
   rev_req_cnt1.PRLD =  GND


 rev_req_sync := /rev_req    
   rev_req_sync.CLKF =  clk7d5	;FCLK/GCK
   rev_req_sync.PRLD =  GND


/stop  =  sw_step_Q
       + /fset * sw_halt_Q    

 sw_sw.T  =  pdata4.PIN * our_addr.LFBK */sw_sw.LFBK * byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q
       + /pdata4.PIN * our_addr.LFBK * sw_sw.LFBK * byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q */reg_num1_Q */reg_num2_Q    
   sw_sw.CLKF =  clk7d5	;FCLK/GCK
   sw_sw.PRLD =  GND


 test_reg0.T  =  pdata0.PIN * our_addr */test_reg0.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       + /pdata0.PIN * our_addr * test_reg0.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q * reg_num2_Q    
   test_reg0.CLKF =  clk7d5	;FCLK/GCK
   test_reg0.PRLD =  GND


 test_reg1.T  =  pdata1.PIN * our_addr */test_reg1.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       + /pdata1.PIN * our_addr * test_reg1.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q * reg_num2_Q    
   test_reg1.CLKF =  clk7d5	;FCLK/GCK
   test_reg1.PRLD =  GND


 test_reg2.T  =  pdata2.PIN * our_addr */test_reg2.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       + /pdata2.PIN * our_addr * test_reg2.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q * reg_num2_Q    
   test_reg2.CLKF =  clk7d5	;FCLK/GCK
   test_reg2.PRLD =  GND


 test_reg3.T  =  pdata3.PIN * our_addr */test_reg3.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q * reg_num2_Q
       + /pdata3.PIN * our_addr * test_reg3.LFBK */byte_cnt0_Q
           */byte_cnt1_Q * data_mode_Q * par_rx_rising_Q * reg_num0_Q
           * reg_num1_Q * reg_num2_Q    
   test_reg3.CLKF =  clk7d5	;FCLK/GCK
   test_reg3.PRLD =  GND


 test_reg4.T  =  pdata4.PIN * our_addr */test_reg4.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q * reg_num2_Q
       + /pdata4.PIN * our_addr * test_reg4.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q * reg_num2_Q    
   test_reg4.CLKF =  clk7d5	;FCLK/GCK
   test_reg4.PRLD =  GND


 test_reg5.T  =  pdata5.PIN * our_addr */test_reg5.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q * reg_num2_Q
       + /pdata5.PIN * our_addr * test_reg5.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q * reg_num2_Q    
   test_reg5.CLKF =  clk7d5	;FCLK/GCK
   test_reg5.PRLD =  GND


 test_reg6.T  =  pdata6.PIN * our_addr */test_reg6.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q * reg_num2_Q
       + /pdata6.PIN * our_addr * test_reg6.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q * reg_num2_Q    
   test_reg6.CLKF =  clk7d5	;FCLK/GCK
   test_reg6.PRLD =  GND


 test_reg7.T  =  pdata7.PIN * our_addr */test_reg7.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q * reg_num2_Q
       + /pdata7.PIN * our_addr * test_reg7.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q * par_rx_rising_Q
           * reg_num0_Q * reg_num1_Q * reg_num2_Q    
   test_reg7.CLKF =  clk7d5	;FCLK/GCK
   test_reg7.PRLD =  GND


 xflag  =  ecp_mode    

 break_done_Q :=  bk_cycle * our_break_del_Q.LFBK    
   break_done_Q.CLKF =  clk7d5	;FCLK/GCK
   break_done_Q.PRLD =  GND


 byte_cnt0_Q.T  =  data_mode_Q * par_rx_rising_Q
       +  byte_cnt0_Q.LFBK */data_mode_Q    
   byte_cnt0_Q.CLKF =  clk7d5	;FCLK/GCK
   byte_cnt0_Q.PRLD =  GND


 byte_cnt1_Q.T  =  byte_cnt1_Q.LFBK */data_mode_Q
       +  byte_cnt0_Q.LFBK * data_mode_Q * par_rx_rising_Q    
   byte_cnt1_Q.CLKF =  clk7d5	;FCLK/GCK
   byte_cnt1_Q.PRLD =  GND


 "cpma_disable_COM/cpma_disable_COM_SETF__$INT"  = /initialize */tp1    

 data_mode_Q :=  ecp_mode * host_ack * ack_rev * our_addr.LFBK
       +  ecp_mode */ack_rev * our_addr.LFBK * periph_ack.LFBK    
   data_mode_Q.CLKF =  clk7d5	;FCLK/GCK
   data_mode_Q.PRLD =  GND


 dbk_data0_Q := /md0 */bk_cycle
       +  bk_cycle * dbk_data0_Q.LFBK    
   dbk_data0_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data0_Q.PRLD =  GND


 dbk_data10_Q := /md10 */bk_cycle
       +  bk_cycle * dbk_data10_Q.LFBK    
   dbk_data10_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data10_Q.PRLD =  GND


 dbk_data11_Q := /md11 */bk_cycle
       +  bk_cycle * dbk_data11_Q.LFBK    
   dbk_data11_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data11_Q.PRLD =  GND


 dbk_data1_Q := /md1 */bk_cycle
       +  bk_cycle * dbk_data1_Q.LFBK    
   dbk_data1_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data1_Q.PRLD =  GND


 dbk_data2_Q := /md2 */bk_cycle.LFBK
       +  bk_cycle.LFBK * dbk_data2_Q.LFBK    
   dbk_data2_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data2_Q.PRLD =  GND


 dbk_data3_Q := /md3 */bk_cycle
       +  bk_cycle * dbk_data3_Q.LFBK    
   dbk_data3_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data3_Q.PRLD =  GND


 dbk_data4_Q := /md4 */bk_cycle
       +  bk_cycle * dbk_data4_Q.LFBK    
   dbk_data4_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data4_Q.PRLD =  GND


 dbk_data5_Q := /md5 */bk_cycle
       +  bk_cycle * dbk_data5_Q.LFBK    
   dbk_data5_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data5_Q.PRLD =  GND


 dbk_data6_Q := /md6 */bk_cycle
       +  bk_cycle * dbk_data6_Q.LFBK    
   dbk_data6_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data6_Q.PRLD =  GND


 dbk_data7_Q := /md7 */bk_cycle
       +  bk_cycle * dbk_data7_Q.LFBK    
   dbk_data7_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data7_Q.PRLD =  GND


 dbk_data8_Q := /md8 */bk_cycle
       +  bk_cycle * dbk_data8_Q.LFBK    
   dbk_data8_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data8_Q.PRLD =  GND


 dbk_data9_Q := /md9 */bk_cycle
       +  bk_cycle * dbk_data9_Q.LFBK    
   dbk_data9_Q.CLKF =  tp3	;FCLK/GCK
   dbk_data9_Q.PRLD =  GND


 delay_cnt0_Q := /delay_cnt0_Q.LFBK * sw_start_d1_Q
       +  delay_cnt1_Q.LFBK * delay_cnt2_Q.LFBK * delay_cnt3_Q.LFBK
           * delay_cnt4_Q.LFBK * delay_cnt5_Q.LFBK * sw_start_d1_Q    
   delay_cnt0_Q.CLKF =  clk7d5	;FCLK/GCK
   delay_cnt0_Q.PRLD =  GND


 delay_cnt1_Q :=  delay_cnt0_Q.LFBK */delay_cnt1_Q.LFBK * sw_start_d1_Q
       + /delay_cnt0_Q.LFBK * delay_cnt1_Q.LFBK * sw_start_d1_Q
       +  delay_cnt0_Q.LFBK * delay_cnt2_Q.LFBK * delay_cnt3_Q.LFBK
           * delay_cnt4_Q.LFBK * delay_cnt5_Q.LFBK * sw_start_d1_Q    
   delay_cnt1_Q.CLKF =  clk7d5	;FCLK/GCK
   delay_cnt1_Q.PRLD =  GND


 delay_cnt2_Q := /delay_cnt0_Q.LFBK * delay_cnt2_Q.LFBK * sw_start_d1_Q
       + /delay_cnt1_Q.LFBK * delay_cnt2_Q.LFBK * sw_start_d1_Q
       +  delay_cnt0_Q.LFBK * delay_cnt1_Q.LFBK */delay_cnt2_Q.LFBK
           * sw_start_d1_Q
       +  delay_cnt2_Q.LFBK * delay_cnt3_Q.LFBK * delay_cnt4_Q.LFBK
           * delay_cnt5_Q.LFBK * sw_start_d1_Q    
   delay_cnt2_Q.CLKF =  clk7d5	;FCLK/GCK
   delay_cnt2_Q.PRLD =  GND


 delay_cnt3_Q.T  =  delay_cnt3_Q.LFBK */sw_start_d1_Q
       +  delay_cnt0_Q.LFBK * delay_cnt1_Q.LFBK * delay_cnt2_Q.LFBK
           */delay_cnt3_Q.LFBK * sw_start_d1_Q
       +  delay_cnt0_Q.LFBK * delay_cnt1_Q.LFBK * delay_cnt2_Q.LFBK
           * delay_cnt3_Q.LFBK */delay_cnt4_Q.LFBK
       +  delay_cnt0_Q.LFBK * delay_cnt1_Q.LFBK * delay_cnt2_Q.LFBK
           * delay_cnt3_Q.LFBK */delay_cnt5_Q.LFBK    
   delay_cnt3_Q.CLKF =  clk7d5	;FCLK/GCK
   delay_cnt3_Q.PRLD =  GND


 delay_cnt4_Q.T  =  delay_cnt4_Q.LFBK */sw_start_d1_Q
       +  delay_cnt0_Q.LFBK * delay_cnt1_Q.LFBK * delay_cnt2_Q.LFBK
           * delay_cnt3_Q.LFBK */delay_cnt4_Q.LFBK * sw_start_d1_Q
       +  delay_cnt0_Q.LFBK * delay_cnt1_Q.LFBK * delay_cnt2_Q.LFBK
           * delay_cnt3_Q.LFBK */delay_cnt5_Q.LFBK * sw_start_d1_Q    
   delay_cnt4_Q.CLKF =  clk7d5	;FCLK/GCK
   delay_cnt4_Q.PRLD =  GND


 delay_cnt5_Q :=  delay_cnt5_Q.LFBK * sw_start_d1_Q
       +  delay_cnt0_Q.LFBK * delay_cnt1_Q.LFBK * delay_cnt2_Q.LFBK
           * delay_cnt3_Q.LFBK * delay_cnt4_Q.LFBK * sw_start_d1_Q    
   delay_cnt5_Q.CLKF =  clk7d5	;FCLK/GCK
   delay_cnt5_Q.PRLD =  GND


 disk_addr0_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data11.PIN * disk_addr0_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data11.PIN */disk_addr0_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data11.PIN * disk_addr0_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data11.PIN */disk_addr0_Q.LFBK    
   disk_addr0_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr0_Q.PRLD =  GND


 disk_addr10_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data1.PIN * disk_addr10_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data1.PIN */disk_addr10_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data1.PIN * disk_addr10_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data1.PIN */disk_addr10_Q.LFBK    
   disk_addr10_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr10_Q.PRLD =  GND


 disk_addr11_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data0.PIN * disk_addr11_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data0.PIN */disk_addr11_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data0.PIN * disk_addr11_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data0.PIN */disk_addr11_Q.LFBK    
   disk_addr11_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr11_Q.PRLD =  GND


 disk_addr1_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data10.PIN * disk_addr1_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data10.PIN */disk_addr1_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data10.PIN * disk_addr1_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data10.PIN */disk_addr1_Q.LFBK    
   disk_addr1_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr1_Q.PRLD =  GND


 disk_addr2_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data9.PIN * disk_addr2_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data9.PIN */disk_addr2_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data9.PIN * disk_addr2_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data9.PIN */disk_addr2_Q.LFBK    
   disk_addr2_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr2_Q.PRLD =  GND


 disk_addr3_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data8.PIN * disk_addr3_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data8.PIN */disk_addr3_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data8.PIN * disk_addr3_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data8.PIN */disk_addr3_Q.LFBK    
   disk_addr3_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr3_Q.PRLD =  GND


 disk_addr4_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data7.PIN * disk_addr4_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data7.PIN */disk_addr4_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data7.PIN * disk_addr4_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data7.PIN */disk_addr4_Q.LFBK    
   disk_addr4_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr4_Q.PRLD =  GND


 disk_addr5_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data6.PIN * disk_addr5_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data6.PIN */disk_addr5_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data6.PIN * disk_addr5_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data6.PIN */disk_addr5_Q.LFBK    
   disk_addr5_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr5_Q.PRLD =  GND


 disk_addr6_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data5.PIN * disk_addr6_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data5.PIN */disk_addr6_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data5.PIN * disk_addr6_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data5.PIN */disk_addr6_Q.LFBK    
   disk_addr6_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr6_Q.PRLD =  GND


 disk_addr7_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data4.PIN * disk_addr7_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data4.PIN */disk_addr7_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data4.PIN * disk_addr7_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data4.PIN */disk_addr7_Q.LFBK    
   disk_addr7_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr7_Q.PRLD =  GND


 disk_addr8_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data3.PIN * disk_addr8_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data3.PIN */disk_addr8_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data3.PIN * disk_addr8_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data3.PIN */disk_addr8_Q.LFBK    
   disk_addr8_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr8_Q.PRLD =  GND


 disk_addr9_Q.T  =  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause * omni_data2.PIN * disk_addr9_Q.LFBK
       +  md10 * md11 * md3 * md4 * md5 * md6 * md7 * md8 * md9
           * pause */omni_data2.PIN */disk_addr9_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause * omni_data2.PIN * disk_addr9_Q.LFBK
       + /md10 */md11 */md3 */md4 */md5 */md6 */md7 */md8 */md9
           */pause */omni_data2.PIN */disk_addr9_Q.LFBK    
   disk_addr9_Q.CLKF =  tp3	;FCLK/GCK
   disk_addr9_Q.PRLD =  GND


/host_clk_cnt0_Q :=  host_clk_d1_Q */host_clk_d2_Q.LFBK
       + /host_clk_d1_Q * host_clk_d2_Q.LFBK
       +  host_clk_cnt0_Q.LFBK */host_clk_cnt1_Q.LFBK    
   host_clk_cnt0_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_cnt0_Q.PRLD =  GND


/host_clk_cnt1_Q :=  host_clk_d1_Q */host_clk_d2_Q.LFBK
       + /host_clk_d1_Q * host_clk_d2_Q.LFBK
       + /host_clk_cnt0_Q.LFBK */host_clk_cnt1_Q.LFBK    
   host_clk_cnt1_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_cnt1_Q.PRLD =  GND


 host_clk_d1_Q := /host_ack */ack_rev.LFBK
       +  host_clk * ack_rev.LFBK    
   host_clk_d1_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_d1_Q.PRLD =  GND


 host_clk_d2_Q :=  host_clk_d1_Q    
   host_clk_d2_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_d2_Q.PRLD =  GND


 latch_led0_Q := /omni_f * sw_rotary0_Q */sw_rotary1_Q * sw_rotary2_Q
       + /md0 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q    
;Imported pterms
       + /ts1 */omni_data0.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /ts1 */omni_data0.PIN */sw_rotary0_Q */sw_rotary1_Q
       + /omni_data0.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q
   latch_led0_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led0_Q.PRLD =  GND


 latch_led10_Q := /md10 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /omni_data10.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q
       + /bk_in_prog * sw_rotary0_Q */sw_rotary1_Q * sw_rotary2_Q    
;Imported pterms
       + /ts1 */omni_data10.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /ts1 */omni_data10.PIN */sw_rotary0_Q */sw_rotary1_Q
   latch_led10_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led10_Q.PRLD =  GND


 latch_led11_Q := /md11 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /ts1 */omni_data11.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /omni_data11.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q
       + /bk_cycle.LFBK * sw_rotary0_Q */sw_rotary1_Q * sw_rotary2_Q    
;Imported pterms
       + /ts1 */omni_data11.PIN */sw_rotary0_Q */sw_rotary1_Q
   latch_led11_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led11_Q.PRLD =  GND


 latch_led1_Q := /omni_d * sw_rotary0_Q */sw_rotary1_Q * sw_rotary2_Q
       + /md1 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /ts1 */omni_data1.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /omni_data1.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q    
;Imported pterms
       + /ts1 */omni_data1.PIN */sw_rotary0_Q */sw_rotary1_Q    
   latch_led1_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led1_Q.PRLD =  GND


 latch_led2_Q := /omni_e * sw_rotary0_Q */sw_rotary1_Q * sw_rotary2_Q
       + /md2 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /ts1 */omni_data2.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /omni_data2.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q    
;Imported pterms
       + /ts1 */omni_data2.PIN */sw_rotary0_Q */sw_rotary1_Q
   latch_led2_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led2_Q.PRLD =  GND


 latch_led3_Q := /ir0 * sw_rotary0_Q */sw_rotary1_Q * sw_rotary2_Q
       + /md3 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /omni_data3.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q    
;Imported pterms
       + /ts1 */omni_data3.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /ts1 */omni_data3.PIN */sw_rotary0_Q */sw_rotary1_Q
   latch_led3_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led3_Q.PRLD =  GND


 latch_led4_Q := /ir1 * sw_rotary0_Q */sw_rotary1_Q * sw_rotary2_Q
       + /md4 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /ts1 */omni_data4.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /omni_data4.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q    
;Imported pterms
       + /ts1 */omni_data4.PIN */sw_rotary0_Q */sw_rotary1_Q
   latch_led4_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led4_Q.PRLD =  GND


 latch_led5_Q := /ir2 * sw_rotary0_Q */sw_rotary1_Q * sw_rotary2_Q
       + /md5 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /ts1 */omni_data5.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /omni_data5.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q    
;Imported pterms
       + /ts1 */omni_data5.PIN */sw_rotary0_Q */sw_rotary1_Q    
   latch_led5_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led5_Q.PRLD =  GND


 latch_led6_Q := /md6 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /ts1 */omni_data6.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /ts1 */omni_data6.PIN */sw_rotary0_Q */sw_rotary1_Q
       + /omni_data6.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q    
;Imported pterms
       + /bk_cycle.LFBK * our_addr * our_break_tp1_Q */reg_num0_Q
           * reg_num1_Q * reg_num2_Q * sw_rotary0_Q */sw_rotary1_Q
           * sw_rotary2_Q
   latch_led6_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led6_Q.PRLD =  GND


 latch_led7_Q := /md7 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /ts1 */omni_data7.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /ts1 */omni_data7.PIN */sw_rotary0_Q */sw_rotary1_Q
       + /omni_data7.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q    
;Imported pterms
       +  sw_cycle_Q */sw_momentary0_Q */sw_momentary1_Q * sw_momentary2_Q
           * sw_rotary0_Q */sw_rotary1_Q * sw_rotary2_Q
   latch_led7_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led7_Q.PRLD =  GND


 latch_led8_Q := /md8 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /ts1 */omni_data8.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /omni_data8.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q
       +  sw_sw * sw_rotary0_Q */sw_rotary1_Q * sw_rotary2_Q    
;Imported pterms
       + /ts1 */omni_data8.PIN */sw_rotary0_Q */sw_rotary1_Q
   latch_led8_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led8_Q.PRLD =  GND


 latch_led9_Q := /pause * sw_rotary0_Q */sw_rotary1_Q * sw_rotary2_Q
       + /md9 */sw_rotary0_Q * sw_rotary1_Q */sw_rotary2_Q
       + /ts1 */omni_data9.PIN * sw_rotary0_Q */sw_rotary2_Q
       + /omni_data9.PIN */sw_rotary0_Q */sw_rotary1_Q */sw_rotary2_Q    
;Imported pterms
       + /ts1 */omni_data9.PIN */sw_rotary0_Q */sw_rotary1_Q
   latch_led9_Q.CLKF =  "latch_led9_Q/latch_led9_Q_CLKF"
   latch_led9_Q.PRLD =  GND


 "latch_led9_Q/latch_led9_Q_CLKF"  =  tp1 * sw_rotary0_Q.LFBK */sw_rotary2_Q.LFBK
       +  clk7d5 * sw_rotary0_Q.LFBK * sw_rotary2_Q.LFBK
       +  clk7d5 */sw_rotary0_Q.LFBK */sw_rotary2_Q.LFBK
       +  clk7d5 */sw_rotary0_Q.LFBK * sw_rotary1_Q.LFBK
       +  tp1 */sw_rotary0_Q.LFBK */sw_rotary1_Q.LFBK * sw_rotary2_Q.LFBK    

 ma_inc_Q :=  break_done_Q.LFBK * our_break_del_Q.LFBK    
   ma_inc_Q.CLKF =  clk7d5	;FCLK/GCK
   ma_inc_Q.PRLD =  GND


 need_break_Q.T  =  our_addr */need_break_Q.LFBK */our_break_del_Q.LFBK
           */read_break_pending_Q.LFBK */reg_num0_Q * reg_num1_Q
           */reg_num2_Q
       +  our_addr * byte_cnt0_Q * data_mode_Q */need_break_Q.LFBK
           * par_rx_rising_Q */reg_num0_Q * reg_num1_Q * reg_num2_Q    
   need_break_Q.CLKF =  clk7d5	;FCLK/GCK
   need_break_Q.RSTF =  tp1 */bk_cycle
   need_break_Q.PRLD =  GND


 "omni_data_out_COM/omni_data_out_COM_D2__$INT"  =  sr_to_data
       + /ts2 */bk_cycle * our_addr */reg_num0_Q * reg_num1_Q
           * reg_num2_Q    

/our_break_del_Q :=  bk_cycle */our_break_del_Q.LFBK
       +  bk_cycle * break_done_Q.LFBK    
   our_break_del_Q.CLKF =  clk7d5	;FCLK/GCK
   our_break_del_Q.PRLD =  GND


 our_break_tp1_Q := /bk_cycle    
   our_break_tp1_Q.CLKF =  tp1
   our_break_tp1_Q.PRLD =  GND


 par_rx_rising_Q :=  periph_ack.LFBK * host_clk_cnt0_Q.LFBK * host_clk_cnt1_Q.LFBK
           * host_clk_d1_Q */host_clk_d2_Q.LFBK    
   par_rx_rising_Q.CLKF =  clk7d5	;FCLK/GCK
   par_rx_rising_Q.PRLD =  GND


 read_break_pending_Q.T  =  break_done_Q.LFBK * our_break_del_Q.LFBK */read_break_pending_Q.LFBK
       +  byte_cnt0_Q * data_mode_Q */our_break_del_Q.LFBK * par_rx_rising_Q
           * read_break_pending_Q.LFBK
       + /break_done_Q.LFBK * byte_cnt0_Q * data_mode_Q * par_rx_rising_Q
           * read_break_pending_Q.LFBK    
   read_break_pending_Q.CLKF =  clk7d5	;FCLK/GCK
   read_break_pending_Q.PRLD =  GND


 reg_num0_Q.T  =  ecp_mode */host_ack * pdata0.PIN * ack_rev.LFBK * par_rx_rising_Q
           */reg_num0_Q.LFBK
       +  ecp_mode */host_ack */pdata0.PIN * ack_rev.LFBK * par_rx_rising_Q
           * reg_num0_Q.LFBK    
   reg_num0_Q.CLKF =  clk7d5	;FCLK/GCK
   reg_num0_Q.PRLD =  GND


 reg_num1_Q.T  =  ecp_mode */host_ack * pdata1.PIN * ack_rev.LFBK * par_rx_rising_Q
           */reg_num1_Q.LFBK
       +  ecp_mode */host_ack */pdata1.PIN * ack_rev.LFBK * par_rx_rising_Q
           * reg_num1_Q.LFBK    
   reg_num1_Q.CLKF =  clk7d5	;FCLK/GCK
   reg_num1_Q.PRLD =  GND


 reg_num2_Q.T  =  ecp_mode */host_ack * pdata2.PIN * ack_rev.LFBK * par_rx_rising_Q
           */reg_num2_Q.LFBK
       +  ecp_mode */host_ack */pdata2.PIN * ack_rev.LFBK * par_rx_rising_Q
           * reg_num2_Q.LFBK    
   reg_num2_Q.CLKF =  clk7d5	;FCLK/GCK
   reg_num2_Q.PRLD =  GND


 sr_to_data  =  sw_cycle_Q */sw_momentary1_Q */sw_momentary2_Q
       + /ts2 * sw_cycle_Q * sw_momentary0_Q */sw_momentary1_Q
       + /md0 * md11 */md1 */md2 */md3 */md9 */omni_f */ts3 * user_mode    

 sw_cycle_Q :=  run */ts1 */sw_momentary1_Q
       +  run */ts1 */sw_momentary2_Q    
   sw_cycle_Q.CLKF =  sw_start_d2_Q
   sw_cycle_Q.RSTF = /sw_start_Q
   sw_cycle_Q.PRLD =  GND


 sw_halt_Q.T  =  pdata6.PIN * our_addr * byte_cnt0_Q */byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           */sw_halt_Q.LFBK
       + /pdata6.PIN * our_addr * byte_cnt0_Q */byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           * sw_halt_Q.LFBK    
   sw_halt_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_halt_Q.PRLD =  GND


 sw_momentary0_Q.T  =  pdata0.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           */sw_momentary0_Q.LFBK
       + /pdata0.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           * sw_momentary0_Q.LFBK    
   sw_momentary0_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_momentary0_Q.PRLD =  GND


 sw_momentary1_Q.T  =  pdata1.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           */sw_momentary1_Q.LFBK
       + /pdata1.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           * sw_momentary1_Q.LFBK    
   sw_momentary1_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_momentary1_Q.PRLD =  GND


 sw_momentary2_Q.T  =  pdata2.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           */sw_momentary2_Q.LFBK
       + /pdata2.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           * sw_momentary2_Q.LFBK    
   sw_momentary2_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_momentary2_Q.PRLD =  GND


 sw_pulse_Q.T  =  sw_pulse_Q.LFBK */sw_start_d1_Q
       + /delay_cnt0_Q.LFBK */delay_cnt1_Q.LFBK * delay_cnt2_Q.LFBK
           */delay_cnt3_Q.LFBK */delay_cnt4_Q.LFBK * delay_cnt5_Q.LFBK
       + /delay_cnt0_Q.LFBK */delay_cnt1_Q.LFBK */delay_cnt2_Q.LFBK
           * delay_cnt3_Q.LFBK */delay_cnt4_Q.LFBK */delay_cnt5_Q.LFBK    
   sw_pulse_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_pulse_Q.PRLD =  GND


 sw_rotary0_Q.T  =  pdata0.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           */sw_rotary0_Q.LFBK
       + /pdata0.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           * sw_rotary0_Q.LFBK    
   sw_rotary0_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_rotary0_Q.PRLD =  GND


 sw_rotary1_Q.T  =  pdata1.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           */sw_rotary1_Q.LFBK
       + /pdata1.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           * sw_rotary1_Q.LFBK    
   sw_rotary1_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_rotary1_Q.PRLD =  GND


 sw_rotary2_Q.T  =  pdata2.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           */sw_rotary2_Q.LFBK
       + /pdata2.PIN * our_addr */byte_cnt0_Q * byte_cnt1_Q * data_mode_Q
           * par_rx_rising_Q * reg_num0_Q */reg_num1_Q */reg_num2_Q
           * sw_rotary2_Q.LFBK    
   sw_rotary2_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_rotary2_Q.PRLD =  GND


 sw_start_Q.T  =  pdata6.PIN * our_addr.LFBK */byte_cnt0_Q * byte_cnt1_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK * reg_num0_Q
           */reg_num1_Q */reg_num2_Q */sw_start_Q.LFBK
       + /pdata6.PIN * our_addr.LFBK */byte_cnt0_Q * byte_cnt1_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK * reg_num0_Q
           */reg_num1_Q */reg_num2_Q * sw_start_Q.LFBK    
   sw_start_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_start_Q.PRLD =  GND


 sw_start_d1_Q := /sw_momentary1_Q * sw_start_Q
       + /sw_momentary2_Q * sw_start_Q    
   sw_start_d1_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_start_d1_Q.PRLD =  GND


 sw_start_d2_Q :=  sw_start_d1_Q    
   sw_start_d2_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_start_d2_Q.PRLD =  GND


 sw_step_Q.T  =  pdata5.PIN * our_addr.LFBK * byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK * reg_num0_Q
           */reg_num1_Q */reg_num2_Q */sw_step_Q.LFBK
       + /pdata5.PIN * our_addr.LFBK * byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q.LFBK * par_rx_rising_Q.LFBK * reg_num0_Q
           */reg_num1_Q */reg_num2_Q * sw_step_Q.LFBK    
   sw_step_Q.CLKF =  clk7d5	;FCLK/GCK
   sw_step_Q.PRLD =  GND


 write_break_pending_Q := /break_done_Q * write_break_pending_Q.LFBK
       +  our_addr * byte_cnt0_Q * data_mode_Q * par_rx_rising_Q
           */reg_num0_Q.LFBK * reg_num1_Q.LFBK * reg_num2_Q.LFBK    
   write_break_pending_Q.CLKF =  clk7d5	;FCLK/GCK
   write_break_pending_Q.PRLD =  GND


****************************  Device Pin Out ****************************

Device : XC95216-15-PQ160


Pin  Signal                          Pin  Signal                        
No.  Name                            No.  Name                          
  1  VCC                              81  VCC                           
  2  test_reg5                        82  break_prio                    
  3  test_reg6                        83  PGND                          
  4  test_reg7                        84  md_dir                        
  5  pdata6                           85  PGND                          
  6  PGND                             86  tp1                           
  7  periph_ack                       87  bk_in_prog                    
  8  PGND                             88  rev_req                       
  9  omni_data0                       89  cpma_disable                  
 10  VCC                              90  pause                         
 11  omni_data5                       91  stop                          
 12  omni_data6                       92  md4                           
 13  omni_data7                       93  periph_req                    
 14  omni_data8                       94  VCC                           
 15  our_addr                         95  md8                           
 16  sw_sw                            96  rev_req_sync                  
 17  md2                              97  md0                           
 18  ma0                              98  ir1                           
 19  ma10                             99  GND                           
 20  GND                             100  GND                           
 21  ma11                            101  ind1                          
 22  ma1                             102  md10                          
 23  ma2                             103  ind2                          
 24  ts1                             104  ts3                           
 25  ma4                             105  PGND                          
 26  ma5                             106  key_cntrl                     
 27  ma7                             107  PGND                          
 28  ma8                             108  ms_ir_dis                     
 29  ma9                             109  PGND                          
 30  ma3                             110  GND                           
 31  GND                             111  xflag                         
 32  pdata0                          112  PGND                          
 33  clk7d5                          113  ack_rev                       
 34  PGND                            114  PGND                          
 35  int_strobe                      115  ts4                           
 36  pdata1                          116  ma_in                         
 37  omni_e                          117  md11                          
 38  pdata4                          118  PGND                          
 39  PGND                            119  rev_req_cnt0                  
 40  GND                             120  GND                           
 41  VCC                             121  VCC                           
 42  tp3                             122  omni_f                        
 43  test_reg0                       123  PGND                          
 44  md7                             124  rev_req_cnt1                  
 45  pdata5                          125  PGND                          
 46  VCC                             126  mem_start                     
 47  omni_data10                     127  GND                           
 48  omni_data11                     128  PGND                          
 49  omni_data1                      129  bk_data_cont                  
 50  omni_data2                      130  PGND                          
 51  GND                             131  init_out                      
 52  omni_data3                      132  PGND                          
 53  omni_data4                      133  load_addr                     
 54  omni_data9                      134  ir2                           
 55  test_reg1                       135  load_addr_en                  
 56  test_reg3                       136  TDO                           
 57  host_clk                        137  GND                           
 58  pdata2                          138  omni_d                        
 59  ts2                             139  user_mode                     
 60  run                             140  ma6                           
 61  VCC                             141  VCC                           
 62  pdata3                          142  md6                           
 63  host_ack                        143  md5                           
 64  tp4                             144  ir0                           
 65  periph_clk                      145  omni_data_in                  
 66  PGND                            146  md1                           
 67  PGND                            147  PGND                          
 68  test_reg2                       148  md9                           
 69  PGND                            149  omni_data_out                 
 70  GND                             150  PGND                          
 71  TDI                             151  PGND                          
 72  ma_ms_load                      152  md3                           
 73  TMS                             153  pdata7                        
 74  PGND                            154  ema0                          
 75  TCK                             155  ema1                          
 76  bk_cycle                        156  ema2                          
 77  fset                            157  VCC                           
 78  our_break                       158  test_reg4                     
 79  ecp_mode                        159  initialize                    
 80  GND                             160  GND                           


Legend : PGND = Tie pin to GND for additional ground path or leave unconnected
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC95216-15-PQ160
Use Timing Constraints                      : ON
Ignore Assignments In Design File           : OFF
Create Programmable Ground Pins             : ON
Use Advanced Fitting                        : ON
Use Local Feedback                          : ON
Use Pin Feedback                            : ON
Default Power Setting                       : STD
Default Output Slew Rate                    : SLOW
Guide File Used                             : NONE
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : ON
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Use Global Nets                             : ON
Collapsing pterm limit                      : 90
Collapsing input limit                      : 36
