 
XACT:  version M1.5.19                           Xilinx Inc.
                                  Fitter Report
   Design Name: power
Fitting Status: Successful                          Date: 11- 5-1998, 10:33PM

****************************  Resource Summary  ****************************

Design        Device            Macrocells     Product Terms   Pins            
Name          Used              Used           Used            Used            
power         XC9572-15-PC84    36 /72  ( 50%) 82 /360 ( 22%)  30 /69  ( 43%) 

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    4           4    |  I/O              :    29       34
Output        :    9           9    |  GCK/IO           :     1        2
Bidirectional :   16          16    |  GTS/IO           :     0        2
GCK           :    1           1    |  GSR/IO           :     0        1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     30          30

GLOBAL RESOURCES:

Signal 'clk7d5' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 0 macrocells in high performance mode (MCHP).
There are 36 macrocells in low power mode (MCLP).
There are a total of 36 macrocells used (MC).

End of Resource Summary
****************************  Errors and Warnings  *************************

WARNING:nd7 - Signal 'FF_relay0_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay1_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay2_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay3_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay4_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay5_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay6_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay7_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
ack_rev             2       7       FB4_4   LOW  SLOW 52   I/O       O
byte_cnt0_Q         2       3       FB1_15  LOW       14   I/O       (b)
byte_cnt1_Q         2       4       FB1_14  LOW       12   GCK/I/O   (b)
data_mode_Q         2       5       FB1_12  LOW       18   I/O       (b)
host_clk_cnt0_Q     3       4       FB1_18  LOW       24   I/O       (b)
host_clk_cnt1_Q     3       4       FB1_17  LOW       15   I/O       (b)
host_clk_d1_Q       2       3       FB1_11  LOW       10   GCK/I/O   (b)
host_clk_d2_Q       1       1       FB4_18  LOW            (b)       (b)
our_addr            5       9       FB1_4   LOW  SLOW 7    I/O       O
par_rx_rising_Q     1       1       FB1_5   LOW       2    I/O       (b)
pdata0              3       4       FB1_7   LOW  SLOW 11   I/O       I/O
pdata1              2       4       FB2_15  LOW  SLOW 83   I/O       I/O
pdata2              3       4       FB3_8   LOW  SLOW 21   I/O       I/O
pdata3              2       4       FB2_2   LOW  SLOW 69   I/O       I/O
pdata4              3       4       FB3_11  LOW  SLOW 33   I/O       I/O
pdata5              2       4       FB2_4   LOW  SLOW 68   I/O       I/O
pdata6              3       4       FB4_1   LOW  SLOW 46   I/O       I/O
pdata7              2       4       FB2_6   LOW  SLOW 71   I/O       I/O
periph_ack          5       13      FB3_15  LOW  SLOW 37   I/O       O
periph_clk          4       7       FB3_5   LOW  SLOW 19   I/O       O
periph_req          2       3       FB2_8   LOW  SLOW 72   I/O       O
reg_num0_Q          2       6       FB1_9   LOW       9    GCK/I/O   GCK
reg_num1_Q          2       6       FB1_8   LOW       5    I/O       I
reg_num2_Q          2       6       FB1_6   LOW       3    I/O       (b)
relay0              2       10      FB4_7   LOW  SLOW 55   I/O       I/O
relay1              2       10      FB4_10  LOW  SLOW 57   I/O       I/O
relay2              2       10      FB4_13  LOW  SLOW 61   I/O       I/O
relay3              2       10      FB1_10  LOW  SLOW 13   I/O       I/O
relay4              2       10      FB1_13  LOW  SLOW 20   I/O       I/O
relay5              2       10      FB1_16  LOW  SLOW 23   I/O       I/O
relay6              2       10      FB1_1   LOW  SLOW 4    I/O       I/O
relay7              2       10      FB4_16  LOW  SLOW 62   I/O       I/O
rev_req_cnt0        2       3       FB2_10  LOW  SLOW 75   I/O       O
rev_req_cnt1        2       3       FB2_12  LOW  SLOW 79   I/O       O
rev_req_sync        1       1       FB2_14  LOW  SLOW 81   I/O       O
xflag               1       1       FB3_12  LOW  SLOW 41   I/O       O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
clk7d5                              FB1_9             9    GCK/I/O   GCK
ecp_mode                            FB4_2             44   I/O       I
host_ack                            FB3_2             17   I/O       I
host_clk                            FB4_11            53   I/O       I
rev_req                             FB1_8             5    I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          16          29          29           37         1/5       18   
FB2           8          12          12           15         4/4       17   
FB3           5          19          19           16         3/2       17   
FB4           7          21          21           14         1/5       17   
            ----                                -----       -----     ----- 
             36                                   82         9/16      69   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               29/7
Number of signals used by logic mapping into function block:  29
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
relay6                2       0     0   3     FB1_1   LOW   4     I/O     I/O
(unused)              0       0     0   5     FB1_2         1     I/O     
(unused)              0       0     0   5     FB1_3         6     I/O     
our_addr              5       0     0   0     FB1_4   LOW   7     I/O     O
par_rx_rising_Q       1       0     0   4     FB1_5   LOW   2     I/O     (b)
reg_num2_Q            2       0     0   3     FB1_6   LOW   3     I/O     (b)
pdata0                3       0     0   2     FB1_7   LOW   11    I/O     I/O
reg_num1_Q            2       0     0   3     FB1_8   LOW   5     I/O     I
reg_num0_Q            2       0     0   3     FB1_9   LOW   9     GCK/I/O GCK
relay3                2       0     0   3     FB1_10  LOW   13    I/O     I/O
host_clk_d1_Q         2       0     0   3     FB1_11  LOW   10    GCK/I/O (b)
data_mode_Q           2       0     0   3     FB1_12  LOW   18    I/O     (b)
relay4                2       0     0   3     FB1_13  LOW   20    I/O     I/O
byte_cnt1_Q           2       0     0   3     FB1_14  LOW   12    GCK/I/O (b)
byte_cnt0_Q           2       0     0   3     FB1_15  LOW   14    I/O     (b)
relay5                2       0     0   3     FB1_16  LOW   23    I/O     I/O
host_clk_cnt1_Q       3       0     0   2     FB1_17  LOW   15    I/O     (b)
host_clk_cnt0_Q       3       0     0   2     FB1_18  LOW   24    I/O     (b)

Signals Used by Logic in Function Block
  1: ack_rev           11: host_clk_d2_Q     21: periph_ack       
  2: byte_cnt0_Q.LFBK  12: our_addr.LFBK     22: reg_num0_Q.LFBK  
  3: byte_cnt1_Q.LFBK  13: par_rx_rising_Q.LFBK 23: reg_num1_Q.LFBK  
  4: data_mode_Q.LFBK  14: pdata0.PIN        24: reg_num2_Q.LFBK  
  5: ecp_mode          15: pdata1.PIN        25: relay0.PIN       
  6: host_ack          16: pdata2.PIN        26: relay3.LFBK      
  7: host_clk          17: pdata3.PIN        27: relay4.LFBK      
  8: host_clk_cnt0_Q.LFBK 18: pdata4.PIN        28: relay5.LFBK      
  9: host_clk_cnt1_Q.LFBK 19: pdata5.PIN        29: relay6.LFBK      
 10: host_clk_d1_Q.LFBK 20: pdata6.PIN       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
relay6               .XXX.......XX......X.XXX....X........... 10      10
our_addr             X...XX.....XX...XXXX.................... 9       9
par_rx_rising_Q      ....................X................... 1       1
reg_num2_Q           X...XX......X..X.......X................ 6       6
pdata0               XXX.....................X............... 4       4
reg_num1_Q           X...XX......X.X.......X................. 6       6
reg_num0_Q           X...XX......XX.......X.................. 6       6
relay3               .XXX.......XX...X....XXX.X.............. 10      10
host_clk_d1_Q        X....XX................................. 3       3
data_mode_Q          X...XX.....X........X................... 5       5
relay4               .XXX.......XX....X...XXX..X............. 10      10
byte_cnt1_Q          .XXX........X........................... 4       4
byte_cnt0_Q          .X.X........X........................... 3       3
relay5               .XXX.......XX.....X..XXX...X............ 10      10
host_clk_cnt1_Q      .......XXXX............................. 4       4
host_clk_cnt0_Q      .......XXXX............................. 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               12/24
Number of signals used by logic mapping into function block:  12
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB2_1         63    I/O     
pdata3                2       0     0   3     FB2_2   LOW   69    I/O     I/O
(unused)              0       0     0   5     FB2_3         67    I/O     
pdata5                2       0     0   3     FB2_4   LOW   68    I/O     I/O
(unused)              0       0     0   5     FB2_5         70    I/O     
pdata7                2       0     0   3     FB2_6   LOW   71    I/O     I/O
(unused)              0       0     0   5     FB2_7         76    GTS/I/O 
periph_req            2       0     0   3     FB2_8   LOW   72    I/O     O
(unused)              0       0     0   5     FB2_9         74    GSR/I/O 
rev_req_cnt0          2       0     0   3     FB2_10  LOW   75    I/O     O
(unused)              0       0     0   5     FB2_11        77    GTS/I/O 
rev_req_cnt1          2       0     0   3     FB2_12  LOW   79    I/O     O
(unused)              0       0     0   5     FB2_13        80    I/O     
rev_req_sync          1       0     0   4     FB2_14  LOW   81    I/O     O
pdata1                2       0     0   3     FB2_15  LOW   83    I/O     I/O
(unused)              0       0     0   5     FB2_16        82    I/O     
(unused)              0       0     0   5     FB2_17        84    I/O     
(unused)              0       0     0   5     FB2_18              (b)     

Signals Used by Logic in Function Block
  1: ack_rev            5: relay1.PIN         9: rev_req          
  2: byte_cnt0_Q        6: relay3.PIN        10: rev_req_cnt0.LFBK
  3: byte_cnt1_Q        7: relay5.PIN        11: rev_req_cnt1.LFBK
  4: reg_num2_Q         8: relay7.PIN        12: rev_req_sync.LFBK

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
pdata3               XXX..X.................................. 4       4
pdata5               XXX...X................................. 4       4
pdata7               XXX....X................................ 4       4
periph_req           .XXX.................................... 3       3
rev_req_cnt0         .........XXX............................ 3       3
rev_req_cnt1         .........XXX............................ 3       3
rev_req_sync         ........X............................... 1       1
pdata1               XXX.X................................... 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               19/17
Number of signals used by logic mapping into function block:  19
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB3_1         25    I/O     
(unused)              0       0     0   5     FB3_2         17    I/O     I
(unused)              0       0     0   5     FB3_3         31    I/O     
(unused)              0       0     0   5     FB3_4         32    I/O     
periph_clk            4       0     0   1     FB3_5   LOW   19    I/O     O
(unused)              0       0     0   5     FB3_6         34    I/O     
(unused)              0       0     0   5     FB3_7         35    I/O     
pdata2                3       0     0   2     FB3_8   LOW   21    I/O     I/O
(unused)              0       0     0   5     FB3_9         26    I/O     
(unused)              0       0     0   5     FB3_10        40    I/O     
pdata4                3       0     0   2     FB3_11  LOW   33    I/O     I/O
xflag                 1       0     0   4     FB3_12  LOW   41    I/O     O
(unused)              0       0     0   5     FB3_13        43    I/O     
(unused)              0       0     0   5     FB3_14        36    I/O     
periph_ack            5       0     0   0     FB3_15  LOW   37    I/O     O
(unused)              0       0     0   5     FB3_16        45    I/O     
(unused)              0       0     0   5     FB3_17        39    I/O     
(unused)              0       0     0   5     FB3_18              (b)     

Signals Used by Logic in Function Block
  1: ack_rev            8: host_clk_d2_Q     14: periph_ack.LFBK  
  2: byte_cnt0_Q        9: our_addr          15: periph_clk.LFBK  
  3: byte_cnt1_Q       10: pdata3.PIN        16: relay2.PIN       
  4: ecp_mode          11: pdata4.PIN        17: relay4.PIN       
  5: host_ack          12: pdata5.PIN        18: rev_req_cnt0     
  6: host_clk_cnt0_Q   13: pdata6.PIN        19: rev_req_cnt1     
  7: host_clk_cnt1_Q  

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
periph_clk           XXX..XXX......X......................... 7       7
pdata2               XXX............X........................ 4       4
pdata4               XXX.............X....................... 4       4
xflag                ...X.................................... 1       1
periph_ack           X...XXXXXXXXXX...XX..................... 13      13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               21/15
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
pdata6                3       0     0   2     FB4_1   LOW   46    I/O     I/O
(unused)              0       0     0   5     FB4_2         44    I/O     I
(unused)              0       0     0   5     FB4_3         51    I/O     
ack_rev               2       0     0   3     FB4_4   LOW   52    I/O     O
(unused)              0       0     0   5     FB4_5         47    I/O     
(unused)              0       0     0   5     FB4_6         54    I/O     
relay0                2       0     0   3     FB4_7   LOW   55    I/O     I/O
(unused)              0       0     0   5     FB4_8         48    I/O     
(unused)              0       0     0   5     FB4_9         50    I/O     
relay1                2       0     0   3     FB4_10  LOW   57    I/O     I/O
(unused)              0       0     0   5     FB4_11        53    I/O     I
(unused)              0       0     0   5     FB4_12        58    I/O     
relay2                2       0     0   3     FB4_13  LOW   61    I/O     I/O
(unused)              0       0     0   5     FB4_14        56    I/O     
(unused)              0       0     0   5     FB4_15        65    I/O     
relay7                2       0     0   3     FB4_16  LOW   62    I/O     I/O
(unused)              0       0     0   5     FB4_17        66    I/O     
host_clk_d2_Q         1       0     0   4     FB4_18  LOW         (b)     (b)

Signals Used by Logic in Function Block
  1: ack_rev.LFBK       8: pdata0.PIN        15: relay0.LFBK      
  2: byte_cnt0_Q        9: pdata1.PIN        16: relay1.LFBK      
  3: byte_cnt1_Q       10: pdata2.PIN        17: relay2.LFBK      
  4: data_mode_Q       11: pdata7.PIN        18: relay6.PIN       
  5: host_clk_d1_Q     12: reg_num0_Q        19: relay7.LFBK      
  6: our_addr          13: reg_num1_Q        20: rev_req_cnt0     
  7: par_rx_rising_Q   14: reg_num2_Q        21: rev_req_cnt1     

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
pdata6               XXX..............X...................... 4       4
ack_rev              X....X.....XXX.....XX................... 7       7
relay0               .XXX.XXX...XXXX......................... 10      10
relay1               .XXX.XX.X..XXX.X........................ 10      10
relay2               .XXX.XX..X.XXX..X....................... 10      10
relay7               .XXX.XX...XXXX....X..................... 10      10
host_clk_d2_Q        ....X................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

/pdata0  =  byte_cnt1_Q.LFBK
       +  relay0.PIN */byte_cnt0_Q.LFBK    
   pdata0.TRST = /ack_rev

 pdata1  = /relay1.PIN */byte_cnt0_Q */byte_cnt1_Q    
   pdata1.TRST = /ack_rev

/pdata2  =  byte_cnt1_Q
       +  relay2.PIN */byte_cnt0_Q    
   pdata2.TRST = /ack_rev

 pdata3  = /relay3.PIN */byte_cnt0_Q */byte_cnt1_Q    
   pdata3.TRST = /ack_rev

/pdata4  =  byte_cnt1_Q
       +  relay4.PIN */byte_cnt0_Q    
   pdata4.TRST = /ack_rev

 pdata5  = /relay5.PIN */byte_cnt0_Q */byte_cnt1_Q    
   pdata5.TRST = /ack_rev

/pdata6  =  byte_cnt1_Q
       +  relay6.PIN */byte_cnt0_Q    
   pdata6.TRST = /ack_rev.LFBK

 pdata7  = /relay7.PIN */byte_cnt0_Q */byte_cnt1_Q    
   pdata7.TRST = /ack_rev

 relay0.T  =  pdata0.PIN * relay0.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q
       + /pdata0.PIN */relay0.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q    
   relay0.CLKF =  clk7d5	;FCLK/GCK
   relay0.PRLD =  VCC


 relay1.T  =  pdata1.PIN * relay1.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q
       + /pdata1.PIN */relay1.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q    
   relay1.CLKF =  clk7d5	;FCLK/GCK
   relay1.PRLD =  VCC


 relay2.T  =  pdata2.PIN * relay2.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q
       + /pdata2.PIN */relay2.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q    
   relay2.CLKF =  clk7d5	;FCLK/GCK
   relay2.PRLD =  VCC


 relay3.T  =  pdata3.PIN * relay3.LFBK * our_addr.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK */reg_num1_Q.LFBK */reg_num2_Q.LFBK
       + /pdata3.PIN */relay3.LFBK * our_addr.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK */reg_num1_Q.LFBK */reg_num2_Q.LFBK    
   relay3.CLKF =  clk7d5	;FCLK/GCK
   relay3.PRLD =  VCC


 relay4.T  =  pdata4.PIN * relay4.LFBK * our_addr.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK */reg_num1_Q.LFBK */reg_num2_Q.LFBK
       + /pdata4.PIN */relay4.LFBK * our_addr.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK */reg_num1_Q.LFBK */reg_num2_Q.LFBK    
   relay4.CLKF =  clk7d5	;FCLK/GCK
   relay4.PRLD =  VCC


 relay5.T  =  pdata5.PIN * relay5.LFBK * our_addr.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK */reg_num1_Q.LFBK */reg_num2_Q.LFBK
       + /pdata5.PIN */relay5.LFBK * our_addr.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK */reg_num1_Q.LFBK */reg_num2_Q.LFBK    
   relay5.CLKF =  clk7d5	;FCLK/GCK
   relay5.PRLD =  VCC


 relay6.T  =  pdata6.PIN * relay6.LFBK * our_addr.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK */reg_num1_Q.LFBK */reg_num2_Q.LFBK
       + /pdata6.PIN */relay6.LFBK * our_addr.LFBK */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK */reg_num1_Q.LFBK */reg_num2_Q.LFBK    
   relay6.CLKF =  clk7d5	;FCLK/GCK
   relay6.PRLD =  VCC


 relay7.T  =  pdata7.PIN * relay7.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q
       + /pdata7.PIN */relay7.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q    
   relay7.CLKF =  clk7d5	;FCLK/GCK
   relay7.PRLD =  VCC


 ack_rev.T  = /ack_rev.LFBK */rev_req_cnt0 */rev_req_cnt1
       +  ack_rev.LFBK * our_addr * rev_req_cnt0 * rev_req_cnt1
           */reg_num0_Q */reg_num1_Q * reg_num2_Q    
   ack_rev.CLKF =  clk7d5	;FCLK/GCK
   ack_rev.PRLD =  GND


 our_addr.T  =  ecp_mode */host_ack * pdata4.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q.LFBK
       +  ecp_mode */host_ack */pdata3.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q.LFBK
       +  ecp_mode */host_ack * pdata6.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q.LFBK
       +  ecp_mode */host_ack * pdata5.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q.LFBK
       +  ecp_mode */host_ack * pdata3.PIN */pdata4.PIN */pdata5.PIN
           */pdata6.PIN * ack_rev */our_addr.LFBK * par_rx_rising_Q.LFBK    
   our_addr.CLKF =  clk7d5	;FCLK/GCK
   our_addr.PRLD =  GND


 periph_ack.T  = /ack_rev */periph_ack.LFBK
       + /ack_rev */rev_req_cnt0 */rev_req_cnt1
       +  ack_rev * periph_ack.LFBK * host_clk_cnt0_Q * host_clk_cnt1_Q
           * host_clk_d2_Q
       +  our_addr */periph_ack.LFBK * host_clk_cnt0_Q * host_clk_cnt1_Q
           */host_clk_d2_Q
       + /host_ack * pdata3.PIN */pdata4.PIN */pdata5.PIN */pdata6.PIN
           */periph_ack.LFBK * host_clk_cnt0_Q * host_clk_cnt1_Q
           */host_clk_d2_Q    
   periph_ack.CLKF =  clk7d5	;FCLK/GCK
   periph_ack.PRLD =  GND


 periph_clk.T  =  ack_rev */periph_clk.LFBK
       + /ack_rev * periph_clk.LFBK * host_clk_cnt0_Q * host_clk_cnt1_Q
           * host_clk_d2_Q
       + /periph_clk.LFBK */byte_cnt1_Q * host_clk_cnt0_Q * host_clk_cnt1_Q
           */host_clk_d2_Q
       + /periph_clk.LFBK */byte_cnt0_Q * host_clk_cnt0_Q * host_clk_cnt1_Q
           */host_clk_d2_Q    
   periph_clk.CLKF =  clk7d5	;FCLK/GCK
   periph_clk.PRLD =  GND


/periph_req  = /byte_cnt1_Q * reg_num2_Q
       + /byte_cnt0_Q * reg_num2_Q    

/rev_req_cnt0.T  =  rev_req_cnt0.LFBK * rev_req_cnt1.LFBK * rev_req_sync.LFBK
       + /rev_req_cnt0.LFBK */rev_req_cnt1.LFBK */rev_req_sync.LFBK    
   rev_req_cnt0.CLKF =  clk7d5	;FCLK/GCK
   rev_req_cnt0.PRLD =  GND


 rev_req_cnt1.T  =  rev_req_cnt0.LFBK */rev_req_cnt1.LFBK * rev_req_sync.LFBK
       + /rev_req_cnt0.LFBK * rev_req_cnt1.LFBK */rev_req_sync.LFBK    
   rev_req_cnt1.CLKF =  clk7d5	;FCLK/GCK
   rev_req_cnt1.PRLD =  GND


 rev_req_sync := /rev_req    
   rev_req_sync.CLKF =  clk7d5	;FCLK/GCK
   rev_req_sync.PRLD =  GND


 xflag  =  ecp_mode    

 byte_cnt0_Q.T  =  byte_cnt0_Q.LFBK */data_mode_Q.LFBK
       +  data_mode_Q.LFBK * par_rx_rising_Q.LFBK    
   byte_cnt0_Q.CLKF =  clk7d5	;FCLK/GCK
   byte_cnt0_Q.PRLD =  GND


 byte_cnt1_Q.T  =  byte_cnt1_Q.LFBK */data_mode_Q.LFBK
       +  byte_cnt0_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK    
   byte_cnt1_Q.CLKF =  clk7d5	;FCLK/GCK
   byte_cnt1_Q.PRLD =  GND


 data_mode_Q :=  ecp_mode * host_ack * ack_rev * our_addr.LFBK
       +  ecp_mode */ack_rev * our_addr.LFBK * periph_ack    
   data_mode_Q.CLKF =  clk7d5	;FCLK/GCK
   data_mode_Q.PRLD =  GND


/host_clk_cnt0_Q := /host_clk_d1_Q.LFBK * host_clk_d2_Q
       +  host_clk_d1_Q.LFBK */host_clk_d2_Q
       +  host_clk_cnt0_Q.LFBK */host_clk_cnt1_Q.LFBK    
   host_clk_cnt0_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_cnt0_Q.PRLD =  GND


/host_clk_cnt1_Q := /host_clk_d1_Q.LFBK * host_clk_d2_Q
       +  host_clk_d1_Q.LFBK */host_clk_d2_Q
       + /host_clk_cnt0_Q.LFBK */host_clk_cnt1_Q.LFBK    
   host_clk_cnt1_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_cnt1_Q.PRLD =  GND


 host_clk_d1_Q := /host_ack */ack_rev
       +  host_clk * ack_rev    
   host_clk_d1_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_d1_Q.PRLD =  GND


 host_clk_d2_Q :=  host_clk_d1_Q    
   host_clk_d2_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_d2_Q.PRLD =  GND


 par_rx_rising_Q :=  periph_ack    
   par_rx_rising_Q.CLKF =  clk7d5	;FCLK/GCK
   par_rx_rising_Q.PRLD =  GND


 reg_num0_Q.T  =  ecp_mode */host_ack * pdata0.PIN * ack_rev * par_rx_rising_Q.LFBK
           */reg_num0_Q.LFBK
       +  ecp_mode */host_ack */pdata0.PIN * ack_rev * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK    
   reg_num0_Q.CLKF =  clk7d5	;FCLK/GCK
   reg_num0_Q.PRLD =  GND


 reg_num1_Q.T  =  ecp_mode */host_ack * pdata1.PIN * ack_rev * par_rx_rising_Q.LFBK
           */reg_num1_Q.LFBK
       +  ecp_mode */host_ack */pdata1.PIN * ack_rev * par_rx_rising_Q.LFBK
           * reg_num1_Q.LFBK    
   reg_num1_Q.CLKF =  clk7d5	;FCLK/GCK
   reg_num1_Q.PRLD =  GND


 reg_num2_Q.T  =  ecp_mode */host_ack * pdata2.PIN * ack_rev * par_rx_rising_Q.LFBK
           */reg_num2_Q.LFBK
       +  ecp_mode */host_ack */pdata2.PIN * ack_rev * par_rx_rising_Q.LFBK
           * reg_num2_Q.LFBK    
   reg_num2_Q.CLKF =  clk7d5	;FCLK/GCK
   reg_num2_Q.PRLD =  GND


****************************  Device Pin Out ****************************

Device : XC9572-15-PC84


                                                       r     r           r  
                                                       e     e           e  
                                                       v     v           v  
                                                       _     _           _  
                         o                             r     r           r  
                         u     r                       e     e           e  
             p     c     r     e  r              p     q     q           q  
             d     l     _     v  e              d     _     _           _  
             a     k     a     _  l              a     s     c           c  
             t  T  7  G  d  T  r  a  T  T  T  T  t  T  y  T  n  V  T  T  n  
             a  I  d  N  d  I  e  y  I  I  I  I  a  I  n  I  t  C  I  I  t  
             0  E  5  D  r  E  q  6  E  E  E  E  1  E  c  E  1  C  E  E  0  
             --------------------------------------------------------------  
            /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
       TIE | 12                                                          74 | TIE
    relay3 | 13                                                          73 | VCC
       TIE | 14                                                          72 | periph_req
       TIE | 15                                                          71 | pdata7
       GND | 16                                                          70 | TIE
  host_ack | 17                                                          69 | pdata3
       TIE | 18                                                          68 | pdata5
periph_clk | 19                                                          67 | TIE
    relay4 | 20                                                          66 | TIE
    pdata2 | 21                       XC9572-15-PC84                     65 | TIE
       VCC | 22                                                          64 | VCC
    relay5 | 23                                                          63 | TIE
       TIE | 24                                                          62 | relay7
       TIE | 25                                                          61 | relay2
       TIE | 26                                                          60 | GND
       GND | 27                                                          59 | TDO
       TDI | 28                                                          58 | TIE
       TMS | 29                                                          57 | relay1
       TCK | 30                                                          56 | TIE
       TIE | 31                                                          55 | relay0
       TIE | 32                                                          54 | TIE
           \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
             --------------------------------------------------------------  
             p  T  T  T  p  V  T  T  x  G  T  e  T  p  T  T  G  T  T  a  h  
             d  I  I  I  e  C  I  I  f  N  I  c  I  d  I  I  N  I  I  c  o  
             a  E  E  E  r  C  E  E  l  D  E  p  E  a  E  E  D  E  E  k  s  
             t           i           a        _     t                 _  t  
             a           p           g        m     a                 r  _  
             4           h                    o     6                 e  c  
                         _                    d                       v  l  
                         a                    e                          k  
                         c                                                  
                         k                                                  


Legend : TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC9572-15-PC84
Use Timing Constraints                      : ON
Ignore Assignments In Design File           : OFF
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : ON
Use Pin Feedback                            : ON
Default Power Setting                       : LOW
Default Output Slew Rate                    : SLOW
Guide File Used                             : NONE
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : ON
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Use Global Nets                             : ON
Collapsing pterm limit                      : 90
Collapsing input limit                      : 36
