 
XACT:  version M1.5.19                           Xilinx Inc.
                                  Fitter Report
   Design Name: power
Fitting Status: Successful                          Date: 11- 5-1998, 10:39PM

****************************  Resource Summary  ****************************

Design        Device            Macrocells     Product Terms   Pins            
Name          Used              Used           Used            Used            
power         XC9572-15-PC84    36 /72  ( 50%) 82 /360 ( 22%)  30 /69  ( 43%) 

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    4           4    |  I/O              :    29       34
Output        :    9           9    |  GCK/IO           :     1        2
Bidirectional :   16          16    |  GTS/IO           :     0        2
GCK           :    1           1    |  GSR/IO           :     0        1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     30          30

GLOBAL RESOURCES:

Signal 'clk7d5' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 0 macrocells in high performance mode (MCHP).
There are 36 macrocells in low power mode (MCLP).
There are a total of 36 macrocells used (MC).

End of Resource Summary
****************************  Errors and Warnings  *************************

WARNING:nd7 - Signal 'FF_relay0_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay1_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay2_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay3_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay4_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay5_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay6_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
WARNING:nd7 - Signal 'FF_relay7_I_1/U1/Q/FDCP.TRST' evaluates to 'VCC'.
  The signal is removed.
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
ack_rev             2       7       FB3_1   LOW  SLOW 25   I/O       O
byte_cnt0_Q         2       3       FB4_16  LOW       62   I/O       (b)
byte_cnt1_Q         2       4       FB4_15  LOW       65   I/O       (b)
data_mode_Q         2       5       FB4_14  LOW       56   I/O       (b)
host_clk_cnt0_Q     3       4       FB4_18  LOW            (b)       (b)
host_clk_cnt1_Q     3       4       FB4_17  LOW       66   I/O       (b)
host_clk_d1_Q       2       3       FB4_12  LOW       58   I/O       (b)
host_clk_d2_Q       1       1       FB4_8   LOW       48   I/O       (b)
our_addr            5       9       FB2_3   LOW  SLOW 67   I/O       O
par_rx_rising_Q     1       1       FB4_6   LOW       54   I/O       (b)
pdata0              3       4       FB3_4   LOW  SLOW 32   I/O       I/O
pdata1              2       4       FB2_1   LOW  SLOW 63   I/O       I/O
pdata2              3       4       FB2_4   LOW  SLOW 68   I/O       I/O
pdata3              2       4       FB2_6   LOW  SLOW 71   I/O       I/O
pdata4              3       4       FB2_8   LOW  SLOW 72   I/O       I/O
pdata5              2       4       FB2_12  LOW  SLOW 79   I/O       I/O
pdata6              3       4       FB2_15  LOW  SLOW 83   I/O       I/O
pdata7              2       4       FB2_17  LOW  SLOW 84   I/O       I/O
periph_ack          5       13      FB4_3   LOW  SLOW 51   I/O       O
periph_clk          4       7       FB4_7   LOW  SLOW 55   I/O       O
periph_req          2       3       FB3_13  LOW  SLOW 43   I/O       O
reg_num0_Q          2       6       FB4_11  LOW       53   I/O       I
reg_num1_Q          2       6       FB4_10  LOW       57   I/O       (b)
reg_num2_Q          2       6       FB4_9   LOW       50   I/O       (b)
relay0              2       10      FB1_1   LOW  SLOW 4    I/O       I/O
relay1              2       10      FB1_4   LOW  SLOW 7    I/O       I/O
relay2              2       10      FB1_7   LOW  SLOW 11   I/O       I/O
relay3              2       10      FB3_7   LOW  SLOW 35   I/O       I/O
relay4              2       10      FB4_13  LOW  SLOW 61   I/O       I/O
relay5              2       10      FB1_12  LOW  SLOW 18   I/O       I/O
relay6              2       10      FB1_16  LOW  SLOW 23   I/O       I/O
relay7              2       10      FB3_10  LOW  SLOW 40   I/O       I/O
rev_req_cnt0        2       3       FB4_1   LOW  SLOW 46   I/O       O
rev_req_cnt1        2       3       FB1_3   LOW  SLOW 6    I/O       O
rev_req_sync        1       1       FB1_10  LOW  SLOW 13   I/O       O
xflag               1       1       FB3_16  LOW  SLOW 45   I/O       O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
clk7d5                              FB1_9             9    GCK/I/O   GCK
ecp_mode                            FB4_2             44   I/O       I
host_ack                            FB3_2             17   I/O       I
host_clk                            FB4_11            53   I/O       I
rev_req                             FB3_11            33   I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           7          22          22           13         2/5       18   
FB2           8          18          18           22         1/7       17   
FB3           6          17          17           12         3/3       17   
FB4          15          29          29           35         3/1       17   
            ----                                -----       -----     ----- 
             36                                   82         9/16      69   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               22/14
Number of signals used by logic mapping into function block:  22
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
relay0                2       0     0   3     FB1_1   LOW   4     I/O     I/O
(unused)              0       0     0   5     FB1_2         1     I/O     
rev_req_cnt1          2       0     0   3     FB1_3   LOW   6     I/O     O
relay1                2       0     0   3     FB1_4   LOW   7     I/O     I/O
(unused)              0       0     0   5     FB1_5         2     I/O     
(unused)              0       0     0   5     FB1_6         3     I/O     
relay2                2       0     0   3     FB1_7   LOW   11    I/O     I/O
(unused)              0       0     0   5     FB1_8         5     I/O     
(unused)              0       0     0   5     FB1_9         9     GCK/I/O GCK
rev_req_sync          1       0     0   4     FB1_10  LOW   13    I/O     O
(unused)              0       0     0   5     FB1_11        10    GCK/I/O 
relay5                2       0     0   3     FB1_12  LOW   18    I/O     I/O
(unused)              0       0     0   5     FB1_13        20    I/O     
(unused)              0       0     0   5     FB1_14        12    GCK/I/O 
(unused)              0       0     0   5     FB1_15        14    I/O     
relay6                2       0     0   3     FB1_16  LOW   23    I/O     I/O
(unused)              0       0     0   5     FB1_17        15    I/O     
(unused)              0       0     0   5     FB1_18        24    I/O     

Signals Used by Logic in Function Block
  1: byte_cnt0_Q        9: pdata5.PIN        16: relay2.LFBK      
  2: byte_cnt1_Q       10: pdata6.PIN        17: relay5.LFBK      
  3: data_mode_Q       11: reg_num0_Q        18: relay6.LFBK      
  4: our_addr          12: reg_num1_Q        19: rev_req          
  5: par_rx_rising_Q   13: reg_num2_Q        20: rev_req_cnt0     
  6: pdata0.PIN        14: relay0.LFBK       21: rev_req_cnt1.LFBK
  7: pdata1.PIN        15: relay1.LFBK       22: rev_req_sync.LFBK
  8: pdata2.PIN       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
relay0               XXXXXX....XXXX.......................... 10      10
rev_req_cnt1         ...................XXX.................. 3       3
relay1               XXXXX.X...XXX.X......................... 10      10
relay2               XXXXX..X..XXX..X........................ 10      10
rev_req_sync         ..................X..................... 1       1
relay5               XXXXX...X.XXX...X....................... 10      10
relay6               XXXXX....XXXX....X...................... 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               18/18
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
pdata1                2       0     0   3     FB2_1   LOW   63    I/O     I/O
(unused)              0       0     0   5     FB2_2         69    I/O     
our_addr              5       0     0   0     FB2_3   LOW   67    I/O     O
pdata2                3       0     0   2     FB2_4   LOW   68    I/O     I/O
(unused)              0       0     0   5     FB2_5         70    I/O     
pdata3                2       0     0   3     FB2_6   LOW   71    I/O     I/O
(unused)              0       0     0   5     FB2_7         76    GTS/I/O 
pdata4                3       0     0   2     FB2_8   LOW   72    I/O     I/O
(unused)              0       0     0   5     FB2_9         74    GSR/I/O 
(unused)              0       0     0   5     FB2_10        75    I/O     
(unused)              0       0     0   5     FB2_11        77    GTS/I/O 
pdata5                2       0     0   3     FB2_12  LOW   79    I/O     I/O
(unused)              0       0     0   5     FB2_13        80    I/O     
(unused)              0       0     0   5     FB2_14        81    I/O     
pdata6                3       0     0   2     FB2_15  LOW   83    I/O     I/O
(unused)              0       0     0   5     FB2_16        82    I/O     
pdata7                2       0     0   3     FB2_17  LOW   84    I/O     I/O
(unused)              0       0     0   5     FB2_18              (b)     

Signals Used by Logic in Function Block
  1: ack_rev            7: par_rx_rising_Q   13: relay2.PIN       
  2: byte_cnt0_Q        8: pdata3.PIN        14: relay3.PIN       
  3: byte_cnt1_Q        9: pdata4.PIN        15: relay4.PIN       
  4: ecp_mode          10: pdata5.PIN        16: relay5.PIN       
  5: host_ack          11: pdata6.PIN        17: relay6.PIN       
  6: our_addr.LFBK     12: relay1.PIN        18: relay7.PIN       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
pdata1               XXX........X............................ 4       4
our_addr             X..XXXXXXXX............................. 9       9
pdata2               XXX.........X........................... 4       4
pdata3               XXX..........X.......................... 4       4
pdata4               XXX...........X......................... 4       4
pdata5               XXX............X........................ 4       4
pdata6               XXX.............X....................... 4       4
pdata7               XXX..............X...................... 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               17/19
Number of signals used by logic mapping into function block:  17
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
ack_rev               2       0     0   3     FB3_1   LOW   25    I/O     O
(unused)              0       0     0   5     FB3_2         17    I/O     I
(unused)              0       0     0   5     FB3_3         31    I/O     
pdata0                3       0     0   2     FB3_4   LOW   32    I/O     I/O
(unused)              0       0     0   5     FB3_5         19    I/O     
(unused)              0       0     0   5     FB3_6         34    I/O     
relay3                2       0     0   3     FB3_7   LOW   35    I/O     I/O
(unused)              0       0     0   5     FB3_8         21    I/O     
(unused)              0       0     0   5     FB3_9         26    I/O     
relay7                2       0     0   3     FB3_10  LOW   40    I/O     I/O
(unused)              0       0     0   5     FB3_11        33    I/O     I
(unused)              0       0     0   5     FB3_12        41    I/O     
periph_req            2       0     0   3     FB3_13  LOW   43    I/O     O
(unused)              0       0     0   5     FB3_14        36    I/O     
(unused)              0       0     0   5     FB3_15        37    I/O     
xflag                 1       0     0   4     FB3_16  LOW   45    I/O     O
(unused)              0       0     0   5     FB3_17        39    I/O     
(unused)              0       0     0   5     FB3_18              (b)     

Signals Used by Logic in Function Block
  1: ack_rev.LFBK       7: par_rx_rising_Q   13: relay0.PIN       
  2: byte_cnt0_Q        8: pdata3.PIN        14: relay3.LFBK      
  3: byte_cnt1_Q        9: pdata7.PIN        15: relay7.LFBK      
  4: data_mode_Q       10: reg_num0_Q        16: rev_req_cnt0     
  5: ecp_mode          11: reg_num1_Q        17: rev_req_cnt1     
  6: our_addr          12: reg_num2_Q       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ack_rev              X....X...XXX...XX....................... 7       7
pdata0               XXX.........X........................... 4       4
relay3               .XXX.XXX.XXX.X.......................... 10      10
relay7               .XXX.XX.XXXX..X......................... 10      10
periph_req           .XX........X............................ 3       3
xflag                ....X................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               29/7
Number of signals used by logic mapping into function block:  29
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
rev_req_cnt0          2       0     0   3     FB4_1   LOW   46    I/O     O
(unused)              0       0     0   5     FB4_2         44    I/O     I
periph_ack            5       0     0   0     FB4_3   LOW   51    I/O     O
(unused)              0       0     0   5     FB4_4         52    I/O     
(unused)              0       0     0   5     FB4_5         47    I/O     
par_rx_rising_Q       1       0     0   4     FB4_6   LOW   54    I/O     (b)
periph_clk            4       0     0   1     FB4_7   LOW   55    I/O     O
host_clk_d2_Q         1       0     0   4     FB4_8   LOW   48    I/O     (b)
reg_num2_Q            2       0     0   3     FB4_9   LOW   50    I/O     (b)
reg_num1_Q            2       0     0   3     FB4_10  LOW   57    I/O     (b)
reg_num0_Q            2       0     0   3     FB4_11  LOW   53    I/O     I
host_clk_d1_Q         2       0     0   3     FB4_12  LOW   58    I/O     (b)
relay4                2       0     0   3     FB4_13  LOW   61    I/O     I/O
data_mode_Q           2       0     0   3     FB4_14  LOW   56    I/O     (b)
byte_cnt1_Q           2       0     0   3     FB4_15  LOW   65    I/O     (b)
byte_cnt0_Q           2       0     0   3     FB4_16  LOW   62    I/O     (b)
host_clk_cnt1_Q       3       0     0   2     FB4_17  LOW   66    I/O     (b)
host_clk_cnt0_Q       3       0     0   2     FB4_18  LOW         (b)     (b)

Signals Used by Logic in Function Block
  1: ack_rev           11: host_clk_d2_Q.LFBK 21: periph_ack.LFBK  
  2: byte_cnt0_Q.LFBK  12: our_addr          22: periph_clk.LFBK  
  3: byte_cnt1_Q.LFBK  13: par_rx_rising_Q.LFBK 23: reg_num0_Q.LFBK  
  4: data_mode_Q.LFBK  14: pdata0.PIN        24: reg_num1_Q.LFBK  
  5: ecp_mode          15: pdata1.PIN        25: reg_num2_Q.LFBK  
  6: host_ack          16: pdata2.PIN        26: relay4.LFBK      
  7: host_clk          17: pdata3.PIN        27: rev_req_cnt0.LFBK
  8: host_clk_cnt0_Q.LFBK 18: pdata4.PIN        28: rev_req_cnt1     
  9: host_clk_cnt1_Q.LFBK 19: pdata5.PIN        29: rev_req_sync     
 10: host_clk_d1_Q.LFBK 20: pdata6.PIN       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
rev_req_cnt0         ..........................XXX........... 3       3
periph_ack           X....X.XX.XX....XXXXX.....XX............ 13      13
par_rx_rising_Q      ....................X................... 1       1
periph_clk           XXX....XX.X..........X.................. 7       7
host_clk_d2_Q        .........X.............................. 1       1
reg_num2_Q           X...XX......X..X........X............... 6       6
reg_num1_Q           X...XX......X.X........X................ 6       6
reg_num0_Q           X...XX......XX........X................. 6       6
host_clk_d1_Q        X....XX................................. 3       3
relay4               .XXX.......XX....X....XXXX.............. 10      10
data_mode_Q          X...XX.....X........X................... 5       5
byte_cnt1_Q          .XXX........X........................... 4       4
byte_cnt0_Q          .X.X........X........................... 3       3
host_clk_cnt1_Q      .......XXXX............................. 4       4
host_clk_cnt0_Q      .......XXXX............................. 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

/pdata0  =  byte_cnt1_Q
       +  relay0.PIN */byte_cnt0_Q    
   pdata0.TRST = /ack_rev.LFBK

 pdata1  = /relay1.PIN */byte_cnt0_Q */byte_cnt1_Q    
   pdata1.TRST = /ack_rev

/pdata2  =  byte_cnt1_Q
       +  relay2.PIN */byte_cnt0_Q    
   pdata2.TRST = /ack_rev

 pdata3  = /relay3.PIN */byte_cnt0_Q */byte_cnt1_Q    
   pdata3.TRST = /ack_rev

/pdata4  =  byte_cnt1_Q
       +  relay4.PIN */byte_cnt0_Q    
   pdata4.TRST = /ack_rev

 pdata5  = /relay5.PIN */byte_cnt0_Q */byte_cnt1_Q    
   pdata5.TRST = /ack_rev

/pdata6  =  byte_cnt1_Q
       +  relay6.PIN */byte_cnt0_Q    
   pdata6.TRST = /ack_rev

 pdata7  = /relay7.PIN */byte_cnt0_Q */byte_cnt1_Q    
   pdata7.TRST = /ack_rev

 relay0.T  =  pdata0.PIN * relay0.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q
       + /pdata0.PIN */relay0.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q    
   relay0.CLKF =  clk7d5	;FCLK/GCK
   relay0.PRLD =  VCC


 relay1.T  =  pdata1.PIN * relay1.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q
       + /pdata1.PIN */relay1.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q    
   relay1.CLKF =  clk7d5	;FCLK/GCK
   relay1.PRLD =  VCC


 relay2.T  =  pdata2.PIN * relay2.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q
       + /pdata2.PIN */relay2.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q    
   relay2.CLKF =  clk7d5	;FCLK/GCK
   relay2.PRLD =  VCC


 relay3.T  =  pdata3.PIN * relay3.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q
       + /pdata3.PIN */relay3.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q    
   relay3.CLKF =  clk7d5	;FCLK/GCK
   relay3.PRLD =  VCC


 relay4.T  =  pdata4.PIN * relay4.LFBK * our_addr */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK */reg_num1_Q.LFBK */reg_num2_Q.LFBK
       + /pdata4.PIN */relay4.LFBK * our_addr */byte_cnt0_Q.LFBK
           */byte_cnt1_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK */reg_num1_Q.LFBK */reg_num2_Q.LFBK    
   relay4.CLKF =  clk7d5	;FCLK/GCK
   relay4.PRLD =  VCC


 relay5.T  =  pdata5.PIN * relay5.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q
       + /pdata5.PIN */relay5.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q    
   relay5.CLKF =  clk7d5	;FCLK/GCK
   relay5.PRLD =  VCC


 relay6.T  =  pdata6.PIN * relay6.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q
       + /pdata6.PIN */relay6.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q    
   relay6.CLKF =  clk7d5	;FCLK/GCK
   relay6.PRLD =  VCC


 relay7.T  =  pdata7.PIN * relay7.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q
       + /pdata7.PIN */relay7.LFBK * our_addr */byte_cnt0_Q */byte_cnt1_Q
           * data_mode_Q * par_rx_rising_Q * reg_num0_Q */reg_num1_Q
           */reg_num2_Q    
   relay7.CLKF =  clk7d5	;FCLK/GCK
   relay7.PRLD =  VCC


 ack_rev.T  = /ack_rev.LFBK */rev_req_cnt0 */rev_req_cnt1
       +  ack_rev.LFBK * our_addr * rev_req_cnt0 * rev_req_cnt1
           */reg_num0_Q */reg_num1_Q * reg_num2_Q    
   ack_rev.CLKF =  clk7d5	;FCLK/GCK
   ack_rev.PRLD =  GND


 our_addr.T  =  ecp_mode */host_ack * pdata4.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q
       +  ecp_mode */host_ack */pdata3.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q
       +  ecp_mode */host_ack * pdata6.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q
       +  ecp_mode */host_ack * pdata5.PIN * ack_rev * our_addr.LFBK
           * par_rx_rising_Q
       +  ecp_mode */host_ack * pdata3.PIN */pdata4.PIN */pdata5.PIN
           */pdata6.PIN * ack_rev */our_addr.LFBK * par_rx_rising_Q    
   our_addr.CLKF =  clk7d5	;FCLK/GCK
   our_addr.PRLD =  GND


 periph_ack.T  = /ack_rev */periph_ack.LFBK
       + /ack_rev */rev_req_cnt0.LFBK */rev_req_cnt1
       +  ack_rev * periph_ack.LFBK * host_clk_cnt0_Q.LFBK * host_clk_cnt1_Q.LFBK
           * host_clk_d2_Q.LFBK
       +  our_addr */periph_ack.LFBK * host_clk_cnt0_Q.LFBK * host_clk_cnt1_Q.LFBK
           */host_clk_d2_Q.LFBK
       + /host_ack * pdata3.PIN */pdata4.PIN */pdata5.PIN */pdata6.PIN
           */periph_ack.LFBK * host_clk_cnt0_Q.LFBK * host_clk_cnt1_Q.LFBK
           */host_clk_d2_Q.LFBK    
   periph_ack.CLKF =  clk7d5	;FCLK/GCK
   periph_ack.PRLD =  GND


 periph_clk.T  =  ack_rev */periph_clk.LFBK
       + /ack_rev * periph_clk.LFBK * host_clk_cnt0_Q.LFBK * host_clk_cnt1_Q.LFBK
           * host_clk_d2_Q.LFBK
       + /periph_clk.LFBK */byte_cnt1_Q.LFBK * host_clk_cnt0_Q.LFBK
           * host_clk_cnt1_Q.LFBK */host_clk_d2_Q.LFBK
       + /periph_clk.LFBK */byte_cnt0_Q.LFBK * host_clk_cnt0_Q.LFBK
           * host_clk_cnt1_Q.LFBK */host_clk_d2_Q.LFBK    
   periph_clk.CLKF =  clk7d5	;FCLK/GCK
   periph_clk.PRLD =  GND


/periph_req  = /byte_cnt1_Q * reg_num2_Q
       + /byte_cnt0_Q * reg_num2_Q    

/rev_req_cnt0.T  =  rev_req_cnt0.LFBK * rev_req_cnt1 * rev_req_sync
       + /rev_req_cnt0.LFBK */rev_req_cnt1 */rev_req_sync    
   rev_req_cnt0.CLKF =  clk7d5	;FCLK/GCK
   rev_req_cnt0.PRLD =  GND


 rev_req_cnt1.T  =  rev_req_cnt0 */rev_req_cnt1.LFBK * rev_req_sync.LFBK
       + /rev_req_cnt0 * rev_req_cnt1.LFBK */rev_req_sync.LFBK    
   rev_req_cnt1.CLKF =  clk7d5	;FCLK/GCK
   rev_req_cnt1.PRLD =  GND


 rev_req_sync := /rev_req    
   rev_req_sync.CLKF =  clk7d5	;FCLK/GCK
   rev_req_sync.PRLD =  GND


 xflag  =  ecp_mode    

 byte_cnt0_Q.T  =  byte_cnt0_Q.LFBK */data_mode_Q.LFBK
       +  data_mode_Q.LFBK * par_rx_rising_Q.LFBK    
   byte_cnt0_Q.CLKF =  clk7d5	;FCLK/GCK
   byte_cnt0_Q.PRLD =  GND


 byte_cnt1_Q.T  =  byte_cnt1_Q.LFBK */data_mode_Q.LFBK
       +  byte_cnt0_Q.LFBK * data_mode_Q.LFBK * par_rx_rising_Q.LFBK    
   byte_cnt1_Q.CLKF =  clk7d5	;FCLK/GCK
   byte_cnt1_Q.PRLD =  GND


 data_mode_Q :=  ecp_mode * host_ack * ack_rev * our_addr
       +  ecp_mode */ack_rev * our_addr * periph_ack.LFBK    
   data_mode_Q.CLKF =  clk7d5	;FCLK/GCK
   data_mode_Q.PRLD =  GND


/host_clk_cnt0_Q :=  host_clk_cnt0_Q.LFBK */host_clk_cnt1_Q.LFBK
       + /host_clk_d1_Q.LFBK * host_clk_d2_Q.LFBK
       +  host_clk_d1_Q.LFBK */host_clk_d2_Q.LFBK    
   host_clk_cnt0_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_cnt0_Q.PRLD =  GND


/host_clk_cnt1_Q := /host_clk_cnt0_Q.LFBK */host_clk_cnt1_Q.LFBK
       + /host_clk_d1_Q.LFBK * host_clk_d2_Q.LFBK
       +  host_clk_d1_Q.LFBK */host_clk_d2_Q.LFBK    
   host_clk_cnt1_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_cnt1_Q.PRLD =  GND


 host_clk_d1_Q := /host_ack */ack_rev
       +  host_clk * ack_rev    
   host_clk_d1_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_d1_Q.PRLD =  GND


 host_clk_d2_Q :=  host_clk_d1_Q.LFBK    
   host_clk_d2_Q.CLKF =  clk7d5	;FCLK/GCK
   host_clk_d2_Q.PRLD =  GND


 par_rx_rising_Q :=  periph_ack.LFBK    
   par_rx_rising_Q.CLKF =  clk7d5	;FCLK/GCK
   par_rx_rising_Q.PRLD =  GND


 reg_num0_Q.T  =  ecp_mode */host_ack * pdata0.PIN * ack_rev * par_rx_rising_Q.LFBK
           */reg_num0_Q.LFBK
       +  ecp_mode */host_ack */pdata0.PIN * ack_rev * par_rx_rising_Q.LFBK
           * reg_num0_Q.LFBK    
   reg_num0_Q.CLKF =  clk7d5	;FCLK/GCK
   reg_num0_Q.PRLD =  GND


 reg_num1_Q.T  =  ecp_mode */host_ack * pdata1.PIN * ack_rev * par_rx_rising_Q.LFBK
           */reg_num1_Q.LFBK
       +  ecp_mode */host_ack */pdata1.PIN * ack_rev * par_rx_rising_Q.LFBK
           * reg_num1_Q.LFBK    
   reg_num1_Q.CLKF =  clk7d5	;FCLK/GCK
   reg_num1_Q.PRLD =  GND


 reg_num2_Q.T  =  ecp_mode */host_ack * pdata2.PIN * ack_rev * par_rx_rising_Q.LFBK
           */reg_num2_Q.LFBK
       +  ecp_mode */host_ack */pdata2.PIN * ack_rev * par_rx_rising_Q.LFBK
           * reg_num2_Q.LFBK    
   reg_num2_Q.CLKF =  clk7d5	;FCLK/GCK
   reg_num2_Q.PRLD =  GND


****************************  Device Pin Out ****************************

Device : XC9572-15-PC84


                              r                                               
                              e                                               
                              v                                               
                              _                                               
                              r                                               
                              e                                               
               r     c     r  q     r           p  p           p              
               e     l     e  _     e           d  d           d              
               l  P  k     l  c  P  l  P  P  P  a  a  P  P  P  a     P  P  P  
               a  G  7  G  a  n  G  a  G  G  G  t  t  G  G  G  t  V  G  G  G  
               y  N  d  N  y  t  N  y  N  N  N  a  a  N  N  N  a  C  N  N  N  
               2  D  5  D  1  1  D  0  D  D  D  7  6  D  D  D  5  C  D  D  D  
               --------------------------------------------------------------  
              /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
        PGND | 12                                                          74 | PGND
rev_req_sync | 13                                                          73 | VCC
        PGND | 14                                                          72 | pdata4
        PGND | 15                                                          71 | pdata3
         GND | 16                                                          70 | PGND
    host_ack | 17                                                          69 | PGND
      relay5 | 18                                                          68 | pdata2
        PGND | 19                                                          67 | our_addr
        PGND | 20                                                          66 | PGND
        PGND | 21                       XC9572-15-PC84                     65 | PGND
         VCC | 22                                                          64 | VCC
      relay6 | 23                                                          63 | pdata1
        PGND | 24                                                          62 | PGND
     ack_rev | 25                                                          61 | relay4
        PGND | 26                                                          60 | GND
         GND | 27                                                          59 | TDO
         TDI | 28                                                          58 | PGND
         TMS | 29                                                          57 | PGND
         TCK | 30                                                          56 | PGND
        PGND | 31                                                          55 | periph_clk
      pdata0 | 32                                                          54 | PGND
             \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
               --------------------------------------------------------------  
               r  P  r  P  P  V  P  r  P  G  p  e  x  r  P  P  G  P  p  P  h  
               e  G  e  G  G  C  G  e  G  N  e  c  f  e  G  G  N  G  e  G  o  
               v  N  l  N  N  C  N  l  N  D  r  p  l  v  N  N  D  N  r  N  s  
               _  D  a  D  D     D  a  D     i  _  a  _  D  D     D  i  D  t  
               r     y              y        p  m  g  r              p     _  
               e     3              7        h  o     e              h     c  
               q                             _  d     q              _     l  
                                             r  e     _              a     k  
                                             e        c              c        
                                             q        n              k        
                                                      t                       
                                                      0                       


Legend : PGND = Tie pin to GND for additional ground path or leave unconnected
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC9572-15-PC84
Use Timing Constraints                      : ON
Ignore Assignments In Design File           : OFF
Create Programmable Ground Pins             : ON
Use Advanced Fitting                        : ON
Use Local Feedback                          : ON
Use Pin Feedback                            : ON
Default Power Setting                       : LOW
Default Output Slew Rate                    : SLOW
Guide File Used                             : F:\power\fpanel.gyd
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : ON
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Use Global Nets                             : ON
Collapsing pterm limit                      : 90
Collapsing input limit                      : 36
